The Research Of Cache Replace Algorithm And Slot Schedule Policy Under SMT Environment

Simultaneous Multithreading (SMT) is an advanced technique. It allows instructions to be issued from multiple threads in every cycle. All the hardware contexts are keeping active and want to fetch enough resource in the SMT processor. So how to distribute these resources between threads to improve the performance of the SMT processor is very important. We all want gain much in the performance with lower resource required. So it's very important to do research in it.This thesis has a detailed analysis on common SMT cache replace strategy and slot schedule strategy, and finds some deficiencies in their design. We propose a new cache replace algorithm, Caducity cache replace algorithm. This cache replace algorithm gains the higher performance than the Random cache replace algorithm. It provides a new choice when we design the cache access unit. In order to make better use of instruction fetch units, we also propose some new strategies, MEMCOUNT policy and PRECOUNT policy, base on cache miss rate and branch predict taken rate. The first policy can gain the higher IPCs than other policies and the second policy can make the use of IFQ (Instruction Fetch Queue) better than other policies.In order to evaluate these strategies effectively, we use SS_SMT simulator and SPECint 95 as our experimental platform. We compare all the cache replace algorithms and all the slot schedule policies on our experimental platform. Because of some insufficiencies in the design of the SS_SMT simulator, we do a lot of researches on the SimpleScalar simulator and SS_SMT simulator and have done some improvement on its infrastructure.