Research Of 3.3kV Classed 4H-SiC MOSFET

As a representative of third-generation wide bandgap semiconductor materials,Silicon Carbide(SiC)is desirable for the merits of high critical breakdown electric field,fast carrier saturation drift velocity,and high thermal conductivity,making it a promising candidate for fabrication of power devices used in high voltage,high temperature,anti-radiation,and high power application areas.SiC can directly generate SiO2 as a gate dielectric material through natural oxidation,which makes it more advantageous in manufacturing Metal Oxide Semiconductor Field Effect Transistors(MOSFETs)than other compound semiconductors.MOSFETs are one kinds of power devices widely used in power electronics field,due to its high input impedance,relative easiness to drive and fast switching frequency.Therefore,SiC MOSFETs have become a research hotspot.Based on the requirements of the Sub-topics of the national key research and development program "High-voltage high-power SiC materials and devices and their applications in power electronic transformers",the main content of this paper is design and research of 3.3kV SiC MOSFETs,including device cells and high-voltage terminals.Taking into account the high voltage,high current and device reliability,and finally complete layout design for fabrication.By numerical simulation software and theoretical analysis,the optimization design of 3.3k V SiC MOSFET cells and terminals is completed from the second chapter to the fifth chapter of this article,which reflects the integrity and systematicness of this work.The main research contents of this article are:1.According to the existing experimental results,the effective carrier mobility at different positions of the device is set in the simulation,then the methods of data fitting and extrapolation are used to calculate the exact numerical value and specific gravity of each resistance component of the device,reducing the errors from general approximation calculation.2.Doping optimization in JFET region of device,and one modulation doping design method is proposed that according to the JFET region gate oxide electric field distribution characteristics.The new method can significantly improve the reliability of devices' gate oxide when the devices achieve the same on-resistance.3.Recognizing that the traditional two-dimensional simulation can only characterize the electrical properties of the stripe cells,the three-dimensional numerical simulation is firstly used to study the electrical properties of the square cells and hexagonal cells,making the simulation results correspond to the actual device cells.For the problem that the square cells' high peak field in gate oxide,the methods of center injection and the interlaced cells layout are proposed.That can achieve good results without adding any process steps and costs,so can be widely used in the industry.4.Finally,a reasonable terminal structure is designed and the layout is drawn according to the specific process flow.Although the research in this thesis is only for 3.3kV SiC MOSFET devices,the design ideas and research methods proposed in this paper are universal.Therefore,this paper may have greater significance and reference value.