Research Of Three-dimensional Lateral Mosfet With Low Resistance Path

The contradiction exists between the specific on-resistance(Ron,sp) and breakdown voltage(BV) in the lateral power MOSFET. The reduced surface field(RESURF) and super junction(SJ) technologies are the commo n methods to improve the tradeoff. Both of them improve the doping concentration of the drift region by enhanced depletion. A new mode of current transport is proposed in this thesis, which forms the majority carrier accumulation layer and breaks the silicon limit of the lateral MOSFET. The current is transported by the low resistance path formed by the accumulation layer together with the neutral drift region. Thus the Ron,sp is significantly reduced. Two types of lateral super junction LDMOS with continuous low resistance path is proposed in this thesis.(1) Super Junction LDMOS with an enhanced-accumulation trench-type extending gate(TEG SJ LDMOS). It features the enhanced-accumulation trench-type extending gate(TEG), which is inserted in the drift region. The TEG consists of the P pillar and the surrounding high-k dielectric. There are two main roles of the TEG. On the one hand, in the on-state, the majority carrier accumulation layer is formed at the interface between the high-k dielectric and the N pillar by the TEG. The high permittivity of the high-k dielectric leads to an enhanced charge accumulation effect. The continuous low resistance path consisted of the majority carrier accumulation layer and the channel is established from the source to the drain. Thus the specific on-resistance is significantly reduced. On the other hand, the high-k dielectric causes an assistant depletion of the drift region, which reshapes the drift region’s electric field. The simulation indicates that the BV of 197 V and the Ron,sp of 1.09 mΩ?cm2 are obtained for the TEG SJ LDMOS.For the substrate-assisted depletion(SAD) effect, two kinds of TEG SJ LDMOS with step-doped pillar are proposed. The first is the TEG SJ LDMOS with step-doped N pillar. The step-doped N pillar effectively suppresses the SAD effect and modulates the surface electric field. The BV is improved from 197 V to 217 V. The second is the TEG SJ LDMOS with step-doped P pillar. The P pillar in the drain is replaced by the lightly doping P1 region. The lightly doping P1 region keeps the charge balance of the super junction through reducing the excessive p-type impurities caused by the SAD effect. The BV of 218 V is obtained.(2) Super Junction LDMOS with an assisted-accumulation extend ing gate(AEG). The feature of these devices is the AEG located on the surface of the device. In the on-state, the electron accumulation layer is formed on the surface of the N pillar and the electron inversion layer is formed on the surface of the P pillar. The continuous low resistance path from the source to the drain is formed by the accumulation layer and inversion layer together with the channel. Thus the Ron,sp is significantly reduced by the low resistance path.In order to improve the BV of the SJ LDMOS, the SJ LDMOS with a step-doped N-buffer(AEG-SNB SJ LDMOS) and the SJ LDMOS with a P buried layer(AEG-PB SJ LDMOS) are discussed. The step-doped N-buffer effectively suppresses the SAD effect by offer the non-uniform compensation charge in the drain and source. By simulation, the AEG-SNB SJ LDMOS achieves a BV of 235 V and a Ron,sp of 2.92 mΩ?cm2. The P buried layer in the source reduces the excessive compensation charge and modulates the surface electric field. It is demonstrated by the simulation that the BV of 220 V and the Ron,sp of 3.05 mΩ?cm2 are obtained for the AEG-PB SJ LDMOS.