Design And Implementation Of Multicore DSP Underlying Drivers In High-Performance Baseband Pool

With the deepening of research on centralized baseband processing pool in C-RAN architecture,the baseband board used to realize high-speed transmission and processing of baseband signal has become the focus of attention.Due to high transmission rate,strong computing power,high processing speed and other advantages,Multi-core DSP has gradually developed into the core processor of baseband board.This thesis as a part of the project "Design of low-power general-purpose processor platform for C-RAN",designing baseband board architecture with high-speed transmission,completing design of DSP underlying drivers,implementing the high-speed interconnect between DSP and other modules inside and outside baseband board as well as PowerPC.The specific work has been done as follows:Firstly,in order to solve problem of high-speed communication of baseband board,baseband board architecture which multi-core DSP TMS320C6670 as the core processor is designed according to the design requirements.The design of high-speed interfaces SRIO,HyperLink and PCIe which are integrated by DSP implement high speed transmission between the inside and outside baseband board.Secondly,in order to realize the data transmission between DSP and FPGA on same baseband board,between DSP and FPGA on different baseband board and between the DSPs on different baseband board,and achieve the goal of data transmission between baseband and RF unit as well as interconnection of baseband board,study the logic layer protocol of SRIO and its working mechanism,design SRIO interface driver with DIO transmission mode.The bandwidth between DSP and FPGA on same baseband board,between DSP and FPGA on different baseband board are 12.2Gbps,11 Gbps,11.2Gbps,and delay are 7.68?s,8.03?s,7.94?s by test,meeting the design requirements which transmission bandwidth is not less than 10 Gbps and delay is not higher than 10?s.Thirdly,aiming at the data interaction between DSPs on same baseband board to achieve the problem of processing the baseband data together with the two DSPs on the board,structure and protocol of the HyperLink interface are studied and the driver of HyperLink interface with EDMA is design.Through verification,the data transmission baseband width between the two DSP on same baseband board reached 16.1Gbps through HyperLink,meeting the demand which transmission bandwidth is not less than 10 Gbps.Finally,in order to implement the communication between DSP and PowerPC to achieve the monitoring of the baseband board,the functional structure and protocol of PCIe interface are studied,and the PCIe interface driver with data transmission using EDMA is designed.Through test,bandwidth of DSP and PowerPC is 1.57 Gbps,achieve the goal which transmission bandwidth is not less than 900 Mbps.Through the research of this subject,the design of the baseband board architecture with high speed transmission is realized finally,and the high speed communication between the DSP and other modules inside and outside baseband board is completed.At present,the baseband board has been applied to the baseband pool of C-RAN successfully.