Design Of Non-volatile SRAM Cell Based On RRAM In 65nm Process

With the rapid development of wearable devices,Internet of Things,cloud computing and big data applications,the technology of always turn on-off computing has gradually become the main direction for solving the problem of battery life of intelligent terminals.Static random access memory,as a core component of a SoC chip,suffers from data loss after power-off.In order to meet the demand of the turn on-off computing,Non-volatile SRAM becomes a research hotspot.RRAM shows strong competitive advantage in NVSRAM due to its good electrical characteristics,small area and good compatibility with Complementary Metal Oxide Semiconductor process.This paper will study the non-volatile SRAM cell based on RRAM in advanced process.On the basis of considering the process fluctuation,Two kinds of structural design are analyzed.First,a multi-threshold voltage structure:the cross-coupled inverter has an asymmetrical threshold voltage.The data of the storage node is not a random state when the system is powered on,and then the node is charged and discharged through the restoration path to achieve the data before system power-off.Second,differential data sensing architecture:the cross-coupled inverter is powered by bit lines.By using special control timing for the BL/BLB bit line during system power-on,the storage node data reaches a predictable state,and then the recovery path is turned on to achieve the data before system power-off.Both of these two architectures adopt the way that the unilateral node accesses the RRAM.The two structures were analyzed,and finally a high reliability novel structure of non-volatile SRAM cell is proposed.In addition,Recovery data can be predicted,and a highly reliable control mechanism is constructed to ensure reliable operation of the system.It provides theoretical guidance for system optimization,and has a profound meaning to the rapid development of China's Internet of things.A lot of simulation data based on SMIC 65nm process nodes shows that the proposed structure can significantly improve the data recovery rate and recovery speed,read and write Static Noise Margin,and reduce the static and dynamic power consumption to a large extent.