| In the multi-core system,the traditional bus-based interconnection structure is more and more unable to meet the inter-core communication demand of multi-core system in terms of expansibility,bandwidth and power consumption.The network on chip becomes an effective way to solve interconnection under multi-core architecture.However,the multi-core system with on-chip interconnection structure needs to communicate through the message mechanism.With the increase of the scale of the network on-chip,the memory access time of the system increases,which restricts the system performance.In this thesis,the on-chip multi-core memory architecture,cache algorithm and the implement of on-chip interconnect structure are analyzed and studied in depth.In the traditional multi-core system of on-chip network,L2 or L3 cache is shared.With the increase of network size,the cost of cache synchronization and the memory access time is larger.In this thesis,we constructed the storage structure of multi-core system based on onchip network,and proposed the shared L2 cache architecture based on cluster through the use of bus and on-chip network hybrid interconnection technology in the case of the same number of cores.The structure scale is shorten to a half,and the average memory access time is reduced.Then the Sniper Multi-Core Simulator is used to verify the architecture.We use 64 processors with a cluster size of 4 to do experiments.The experimental results show that the shared L2 cache architecture based on cluster improves the throughput of the system by 5.89% compared with the L2 cache private scheme,which confirms the feasibility and effectiveness of the architecture.At the same time,for a shared cache,when the program executed in a core has a strong flow memory access patterns or the data set for an application is larger,the core is likely to cause pollution to shared caches,and cause cache thrashing,which leads to the performance degradation of other local friendly programs,and also increases the overall power consumption.In this thesis,a core-aware re-reference interval prediction algorithm CARRIP is proposed,which can record the core's id when the the core accessing shared cache.The algorithm performs pseudo partitioning on the shared cache.In the case of replacement and insertion,we give priority to the cache area occupied by the core,which reduced the interaction due to the different patterns of access between the cores.The experiments show that the CA-RRIP algorithm has a significantly performance improvement compared to LRU and SRRIP for the low data sharing programs under the same conditions.Finally,based on the theoretical research,this thesis designs and realizes the on-chip network interconnection structure for the purpose of implemention of on-chip multi-core system.Firstly,the key technology of network on chip interconnection structure is analyzed and selected,including topology architecture,switching techniques,routing algorithms and flow control.The key to the implemention of network on chip interconnect structure is the design of router.Then this thesis introduces the communication data protocol of the network onchip routing,and the handshake protocol is designed to complete the design of the routing interface,which combines with the global asynchronous local synchronization strategy.And then we modularly design the routing node,and use Verilog to implemente the input control module,synchronous FIFO module,virtual channel control module,virtual channel allocation module and output control module.Finally,on the basis of implementing the routing node,the bottom-up design method is adopted to construct a 4x4 2D-Mesh interconnect structure,and the function of virtual channel application and release,request arbitration and data packet transmission are verified.The experimental results show that the interconnect structure has achieved the desired effect,which lays the foundation for the implemention of multi-core system based on network on chip. |
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