Key Techniques Research And System Design Of Low Power High Speed SAR ADC

With the development of the communications industry,especially in the 5G era of the occasion,the original performance of communication equipment has been unable to meet the growing demand for communications applications.This facilitates the development of communication equipment in a direction that can provide higher communication bandwidth and faster data transfer rates.On the other hand,along with the development of applications such as Internet of Things and mobile devices(such as mobile phones),a single device often has the functions of sensing,computing,communication and so on.The functional integration of the chip is very demanding.In these applications,integrated circuits not only to meet the performance requirements,but also to meet the power requirements.In the CMOS process under the premise of rapid development,the semiconductor feature size is gradually reduced.In this process,digital integrated circuits and analog integrated circuits,compared to better in terms of integration,power consumption and speed and so on.This allows digital integrated circuits to better meet the growing demand for speed,power consumption and integration in practical applications,which also makes the processing of signals at the circuit level gradually shifted from analog to digital.Analog-to-digital converters are circuit systems that convert real-world analog signals into digital signals that can be identified by digital systems as a bridge to connect to analog worlds and digital systems.The performance of analog-to-digital converters tends to be a bottleneck in overall system performance.In this paper,through the high-speed low-power SAR ADC structure and design methods of research,analysis of high-speed low-power SAR ADC in the design of the main problems.Based on the analysis of the existing technology,an improved pre-quantization-bypass capacitor array DAC and bootstrap circuit are proposed for the shortcomings of the previous design.Then,a high-speed and low-power single-channel SAR ADC was designed and verified by 40 nm CMOS technology based on these two technologies.The corresponding technology of this design and its application was verified.The results show that the number of ADCs is 9.09 bit and the SFDR is 73.55 dB at 1.2V supply voltage and 340 MS / s sampling rate.