Single-Channel High-Speed Low-Power Successive Approximation Analog-to-Digital Converter

With the development of communication technology,especially the introduction of5G technology,it is necessary to design a low-power analog-to-digital converter with a sampling rate of gigahertz(GHz)and an effective bit of 6-8 bits to meet the relevant requirements.Pipelined ADC with superior throughput is much popular.However,its high-gain,high-linearity operational amplifier requires higher power consumption and the design becomes more difficult as the technology advances,especially as the power supply voltage decreases.On the other hand,the conversion speed and power consumption of SAR ADCs have been greatly improved with the progress of the process,due to its highly digital characteristics.But each quantization of SAR ADC requires n cycles(n is its resolution),and each conversion is limited by the conversion time of the comparator and the settling time of CDAC.Therefore,the SAR ADC needs to further improve the conversion speed by structure improvement.This thesis uses the comparator alternation technique and improves each module to realize a SAR ADC design with sampling frequency of 500MHz and resolution of 8bit.This thesis first introduces a 10bit,75M SAR ADC design,which uses a Vcm-biased CDAC structure,an asynchronous logic structure and a comparator structure using a dynamic latch with a preamplifier structure,and the ADC is implemented by GF55nm CMOS process.The post-layout simulation results show that the sampling frequency of the design can reach 75M/s at a power supply voltage of 1.2V,the core power consumption of the ADC is only 583.5uW;and when the input signal is close to half of the sampling frequency,the SNDR can reach 56.02dB;FOM _w=15.04fJ/bit.For future testing convenience,the related PCB is also designed.Based on the same process,a high-speed SAR ADC is also designed with a sampling frequency of 500M and 8bit single channel.The design comprehensively considers the conversion time of the comparator and the setup time of the CDAC,by minimizing the capacitance value of the CDAC unit and simplifying the capacitance switch structure to reduce its settling time.Thus its settling time is much lower than the comparator conversion time.The alternate structure is also adopted for the comparator to increase its throughput as well as optimization of its bootstrap switch structure to improve the speed of the entire SAR ADC.The post-layout simulation results show that under 1.2V power supply voltage,the core area of the entire SAR ADC is about 170um×80um;when the input frequency is close to the Nyquist frequency,the effective number of bits is 6.26bit;the spurious-free dynamic range SFDR is 55.91dB,FOM _w=40.19fJ/bit.