Research On Online Evolution Technology Of Digital System Based On Bitstream Relocation Of FPGA

Evolvable Hardware(EHW), the integration of programmable logic device and evolutionary algor ithm, can change its own structure and behavior according to the changing environment, so as to obtain capabilities of self-adaption and fault-tolerance. Currently, the mainstream intr insic EHW platforms are based on Virtual Reconfiguration Circuit(VRC) or Dynamic Partial Reconfiguration(DPR). However, while evolving complex circuits, the VRC-based platform suffers from huge area overhead and circuit delay, while the DPR-based platform need huge memory space to host the bitstream files and the evolution speed is relatively slow. To address these limitations, the techniques of bitstream relocation and discrepancy configuration are adopted to improve the efficiency of the DPR-based EHW platform.The main research works are as follow s:(1) The related works of EHW research, as well as the advantages and disadvantages of different reconfiguration approaches of FPGAs used in EHW are analyzed. And the technique of DPR based on bitstream relocation is selected to implement EHW. A brief introduction about the hardware and software platform is given.Moreover,the bitstream relocation technologies of FPGAs,including the configuration process,the structure and the configuration principles of the configuration bitstream,are analyzed.(2) A system-on-chip capable of bitstream relocation is designed based on DPR technology, with Micro Blaze used as the self-reconfiguration controller. Firstly, the general structure of the system is given. Secondly, the principle of bitstream relocation is analyzed; and the process of the bitstream relocation is given, including the generation of the netlist file, the customization of the reconfigurable IP core, the construction of the hardware platform of the bitstream relocation system, the design of the DPR, the unification of the reconstruction areas, the generation of the bitstream file, the design of the software etc. And an interface for cyclic redundancy check calculation is developed using the Microsoft Foundation class library. Finally, the feasibility of the system's capability of bitstream relocation is verified by the logical operations implemented on the Xilinx Virtex-5 FPGA development board,ML507, and the influence of bitstream relocation technique to the bitstream storage, as well as the time needed for the bitstream relocation is analyzed.(3) The online evolution system of image filters based on the techniques of bitstream relocation and discrepancy configuration is designed, in which Micro Blaze is utilized as the controller, ROM IP cores are customized to save the image data,and the technology of bitstream relocation is used to configure the evolvable IP core that performs the major function of the system dynamically. The overall structure and the hardware design of the system as well as the emplementating result are given. Then a simplif ied gener ic algorism is utilized as the searching engine, and the schemes of chromosome coding, discrepancy configuration, fitness evaluation, as well as the genetic operators are designed.Finally, the system structure and self-evolving mechanisms are verified by the implementation of the online evolution of digital image filters. Results show that the proposed evolution mechanisms can reduce the storage space of bit stream files and accelerate the speed of evolution significantly.