The Research Of Microprocessor Verification Technique Based On Multi-simulator Co-simulation

As general purpose high-performance microprocessor has entered the multicore era, the size of the processor chip increases dramatically, resulting the sharp increase of the complexity of functional verification, to develop a verification platform that can quickly identify the design bug has vital role in shortening the time to market of processors.A Verilog and C simulator based microprocessor verification platform, BugFinder, is designed and implemented in this paper. Using GEM5 simulator, this platform implements a reference model for the microprocessor to be verified. Employing System Verilog DPI, the RTL model for the microprocessor to be verified is connected with the GEM5 reference model. Running the same test program on RTL and GEM5, and comparing the results of each executed instruction between RTL and GEM5, the RTL design bug can be identified immediately when it is triggered by the test program.The contribution of this paper is listed as follows:1. A RTL and C co-simulation verification framework is proposed. This paper analyzes the basic theory, the overall architecture, the synchronization requirements, the communication methond of co-simulation et al.2. Based on the proposed framework, this paper designs a prototype for microprocessor co-simulation verification. This system includes the GEM5 reference model, the RTL information extraction module, the Control module et al. The RTL information extraction module, the Communication mechanism, and the Synchronization mechanism are emphasized.3. This paper evaluates the effectiveness of BugFinder platform through the verification of a real processor and the RTL errors injection. Results showed that BugFinder can quickly identify bugs, significantly accelerating the debugging process.