Design Optimization And Verification Of IALU And Shuffle Unit In M-DSP

Digital Signal Processor(DSP) is widely used in the domain of aerospace,communication stations, etc. Due to the increasing amount of data processing as well as the requirement to enhance the real-time, the high-performance DSP has become a hot topic.M-DSP is a 32-bit high-performance DSP that adopts 11 issue VLIW(Very Long Instruction Word) structure and has powerful parallel computing ability.The frequency of M-DSP can reach 1GHz with 40 nm technology library. Based on the design of M-DSP, this thesis completed the design, verification, optimization and synthesis of the IALU and Shuffle Unit. The main work are as follows:1?The instruction set of a high-performance 32-bit IALU was designed, and two kinds of IALU structure was implemented. One structure was a discrete IALU structure unsing Kogge-Stone tree as the core of adder, which had good timing results and is easy to control power consumption, but whose area was larger; The other was a secondary Carry Look-ahead Adder structure of IALU, this approach implementated most of IALU instruction by reusing adder, and take less area, but the design is complex, and has relatively poor timing. Finally, according to the design requirement of the M-DSP,we chosed the former one.2?At present, the traditional Shuffle Unit used the Load instruction to configure Shuffle mode whose occupies too much resource of system registers and need much time to execute. In order to overcome the above problem, this paper adopts independent Shuffle mode address register and memory bank, and its configuration and the implementation of phase separation Shuffle Unit which had two kinds of instructions SHUFH and SHUFW.3?Verifiction was a very important part of digital circuit design. In this paper we made a detail function verification plan. The plan included module function data,random data, the signal of system level, and analysed coverage information to avoid the blind spot of the design's verification, we established a system level regresive verification environment.Finally, Formality of Synopsys was used to compare the comprehensive Gate-level net talbe and RTL design.4?We described the optimization strategy of IALU including logic optimization and methods of pipeline technology. RTL power consumption optimization strategy was used, including the clock gating, logic reorganization, the operand isolation and status code optimization. Finally, used the Design Compiler(DC) of Synopsys to logical synthesis for IALU and Shuffle unit in 40 nm CMOS technics, both IALU and Shuffle unit could content the frequency of 1GHz.