The Design And Implementation Of High-Peformance Digital Signal Processor

Digital Signal Processor is a real-time and high-speed processing unit for digital signals. In the digital processing field, DSP can achieve high performance, low power and cost, good efficiency for executing instructions. It has been widly used in telecommunications, computers and cosuming electronics at the curret time.The thesis presents an architecture design and implementation of 16-bit general-purpose DSP which has general instruction set. aDSP has super Harvard architecture consists of five data buses and one program bus. The pipeline is 12 stages deep, 2-way VLIW wide and the resource conflict is completely resolved by hardware mechanism. It has two 40-bit MAC units and can execute two MAC operations per cycle.The thesis focuses on the innovative hardware implementations of aDSP architecture. It mainly includes the super Harvard memory architecture, processing unit sharing of CSIC instruction set, processing unit sharing of 2-way VLIW pipeline, the unified implementation of power reducing unit and pipeline protection unit with clock-gating. aDSP has a good tradeoff among area, power, performance and frequency.The thesis discusses some low power design skills used in the pipeline protection. A new clock-gating cell is implemented in the pipeline protection unit after considering the strength and weakness of the existing cells and proven to work well with the pipeline. The pipeline is very complicated due to the complexity of the instruction set. Special implementations should be introduced to share the processing resource and reduce the hardware cost. The pipeline is finally reduced to three branches. Some accelerating methods of data processing have been introduced in the datapath which greatly simplifies the datapath design and reduces the path delay. There are six buses in the Harvard memory architecture. The result of the RTL...