The FPGA Implementation Of Turbo Encoder And Decoder System Based On Ethernet Interface

Turbo code, regarded as one of the greatest achievements in communications at the end of the 20 th century, is an important landmark in channel coding field. It not only has a good performance closed to Shannon limit, but also provides new ideas and methods for studying coding theory. Because of its outstanding error-correcting performance, Turbo code has been employed widely in many fields, and naturally becomes the focus of research. In this thesis we build a hardware communication platform on the basis of the research of Turbo code and its hardware implementation. This platform can facilitate the research of Turbo code.In this thesis, first the principle of Turbo code is systematically studied. We introduce the basic structures of Turbo encoder and decoder, deduce the MAP algorithm, simulate the performance of Turbo code and analyze the factors affecting the decoder performance. Then, we complete the FPGA implementation of Turbo encoder and decoder using the design ideas of sliding window algorithm. Finally, in order to analyze the hardware performance of Turbo code flexibly and effectively, we provide a hardware system solution, in which we build the combined system of Turbo encoder and decoder by Ethernet technology. Using Win Pcap technology and Ethernet interface, we realize the exchange and processing of information between PC and FPGA development board, then complete the FPGA implementation of Turbo encoder and decoder system based on Ethernet interface. In this thesis, we also research the Gigabit Ethernet technology, and complete the FPGA implementation of Gigabit Ethernet interface. During the system test, we give the detailed design and simulation results for each data processing procedure. In order to improve the whole system, we not only consider the set interval of time among transmitted packages, but also introduce the processing of long frame and its design of unpacking and grouping package. Through the above work, we complete the design and simulation of the whole Turbo hardware system, analyze and compare the hardware performance between floating-point processing and fixed-point quantitative processing, and achieve the desired design requirements.