Broadband Wireless Access Network Based On RS Code Research And Implementation Of Error Control Coding

The error-control technique is one of the key techniques to decrease the bit error probability in process of data information transmission.Due to their ability to correct both burst errors and random errors,especially the burst errors,RS codes are widely used in the error-control schemes of data communication systems and computer data recording systems.To meet the ever-increasing demand of higher data processing rate in wide-band wireless access network,in this dissertation the mathematic theory and VLSI implementation structures of RS codes and data interleavers are systematically studied and discussed in depth firstly,then a pipelining and minimized VLSI architecture of modified Euclid algorithm is proposed.An area-efficient and high-speed RS(255,239)codec which is implemented in low-cost Cyclone family FPGA device of Altera company is designed based on the area-efficient and pipelining ME algorithm architecture,and its logic synthesis and simulation results show that this RS(255,239)decoder can make to operate at a higher clock frequency of 204MHz in the Altera's Cyclone Family FPGA implementation and its data processing rate is 1.632Gbits/s.Finally the E3 base station equipment's FEC module of wide-band wireless access network based on the implementation of high-speed RS codec and interleaver is designed.