Design And Verification Of High Speed Interface Based On PCIe

PCI Express,referred to as PCIe, is the third generation high performance I/O bus and interface standard proposed by Intel. PCIe can be used as interconnection between all I/O devices on mobile devices, desktop computers, workstations, servers,communication platforms and so on. It uses a dual channel serial transmission mode based on the LVDS differential signal, which consists of two pairs of differential signals. The 8b/10 b codec mechanism can not only complete the clock mosaic task, but also effectively prevent the frequency drift in receiving PLL. The data transmission in the form of data packet can ensure the reliability and accuracy of the data. These mechanisms enable PCIe to provide high bandwidth for 10GB/s when data is transmitted. High bandwidth and high transmission efficiency make it widely used in communication systems and its development prospects.Based on the high speed transmission characteristics of PCIe, this paper designs a high speed interface for communication between the on-chip processor and chip PCIe device. Interface design based on PCIe core 2.0 and PLB4 Standard Specification, PLB processing module is added to the traditional PCIe interface, which can realize the mutual transformation between the PCIe request and the PLB request. The entire interface module is connected with the processor through the PLB bus, and the other end is connected with the chip PCIe device through the serial interface. The main contents of this paper are as follows:The PCIe protocol is studied, and the mechanism of PCIe is summarized before design. The process and mode of PCIe protocol processing data are studied. Through the study of PCIe system architecture, the application of PCIe interface in system architecture is understood, which provides a theoretical basis for the interface design.In the next place, the design method of "Top-Down" is used to realize the design of the interface. According to the function of the interface module is divided into four parts: PCIe core, user logic module, DMA module and PLB module. PCIe nucleus, this design use the Xilinx IP core in this design mainly completes the data transmission and string conversion, power management, assembly and disassembly of physical layer data packets, data packets, packet error analysis and retransmission. The user logic module is the key link of the PCIe core and the PLB module,it completes the control of PCIe core management register and synchronization of PLB sequence and PCIe sequence. The DMA module is between the PCIe core and user logic, control by the user logic to complete the data handling in high speed between storage and external equipment. The PLB interface module is connected with the PLB bus to realize the conversion between the PLB address space and the PCIe address space in the operation request. The four parts realizes the data transmission between the on-chip processor and the chip PCIe device.The verification for the high speed interface is carried out based on the functional verification. A verification platform is built in the Linux environment. The interface will instantiation between the chip processor model and the PCIe host model, through the two models of the interface module to complete the verification. Verification results show that the correct user logic module configuration register function;DMA module can accomplish the single shot for 256 bytes of data handling function;so then the interface module completed the piece between the processor and external PCIe device data transmission with high speed, rate of 5Gbps and meet the design requirements..