Research On Parallel Processing Of Missile-Borne SAR Based On SYS/BIOS

With the continuous development of radar signal processing technology, designing radar systems, especially synthetic aperture radar(SAR) imaging system, has become a focus in recent years. Due to the complex computation of SAR imaging processing algorithms and the large amount of data, single-core DSP system will be poor heat dissipation, power consumption and high production cost, so the traditional single-core DSP is difficult to meet the demand of the system. The emergence of multi-core DSP made a very big contribution to improve the overall performance of the signal processing system. Compared with the single-core DSP, multi-core DSP can assign tasks to eight cores for processing, its processing speed is relatively fast, and the cost and power consumption is relatively low.Traditional software development model in multi-core DSP application development will encounter many problems, because it does not support multi-threading, and can not allocate task flexibly. At the same time, its inter processor communication mechanism is very simple. Application development model based on SYS/BIOS is a new and easy software development model that can be a good solution to the above problems.In order to give full play to the performance advantages of multi-core DSP and achieve high real-time requirements of SAR imaging algorithms, we research a method of SYS/BIOS application based on TMS320C6678. The research work mainly is divided into the following parts:Firstly, we analyze core architecture, CPU and internal storage structure of TMS320C6678 DSP, research the characteristics and the use method of TMDXEVM6678 L EVM. Secondly, we summarize the features of SYS/BIOS and the relationship between SYS/BIOS and XDCtools. We give software development process based on SYS/BIOS and analyze SYS/BIOS thread scheduling, the principle of let out and preemption and SYS/BIOS boot process. We make a detailed study on IPC and compare Notify with Message Q. Thirdly, we design multi-core parallel architectures, thread communication mechanism, solve the problem of cache coherence and configure SYS/BIOS architecture according to the needs. We summarize optimizing method based on SYS/BIOS, including optimization of the SYS/BIOS configuration, the IPC configuration. Finally, we give SAR imaging algorithm results.In this paper, we study parallel processing method of missile-borne SAR based on SYS/BIOS, configure SYS/BIOS architecture, implement inter processor communication and synchronization successfully by IPC, and providing an optimizing method to obtain a good results.