Reaserach And Implementation Of High-speed Multi-core DSP Image Processing System

With the continuous development of semiconductor technology and the wide application of embedded image processing system.mutli-core DSP technique has become the new development direction of embedded image processing system. For now, many IC companies have released their multi-core DSP products, including TI’s TMS320C66x family of multi-core chips. With its superior processing performance and rich resources on-chip, TMS320C66x has become the preferred seclection of engineers and researchers, and is widely used in many fields,such as security, military, medical and mission-critical,et.This subject designs and implements a small-size image processing platform based on the TMS320C6657.And this hardware platform is capable of multi-core processing and Gigabit Ethernet transmission.Moreover,a moving target detect algorithm is improved to become parallel algorithm based on this platform. Compared with the serial algorithm,the program execution time is reduced by 48%. The concrete work of this paper is as follows:Firstly,this paper introduces TMS320C6657’s composition and characteristics.And it also descripts multi-core software’s development methods, design rules and program optimization.Then a detailed description of hardware design of this platform is given,including the realization of each module,such as chip selection,power supply design and peripheral circuits,etc.Secondly,this article describes multi-core DSP’s ethernet communication and inter-processor communication,and applys both to the ethernet transfer performance test and image edge detection testThe test results not only shows that the ethernet interface’s transmission speed is greater than 900Mbps,but also proves that the feasibility of inter-processor communication scheme of this paper.Finally,based on the above two aspects,this paper has made some parallel improvements on a moving target detection algorithm,including re-assigned tasks, the distribution and use of on-chip memory and using a variety of program optimization methods, such as library functions, loop unrolling and set the compiler optimization levels.Ultimately, this algorithm’s performance has been significantly improved. Compared with the serial algorithm, the execution time is reduced from 7.78ms to 4.05ms.