A Design Of A Analog Front-End For ECG Chip

In recent years, with the development of the medical science, people need to early diagnosis and timely treatment by medical equipment, and real-time monitor the patient’s body. In order to meet this urgent demand, wearable medical devices research is becoming more and more attention by people, because this kind of equipment allow patients to monitor their body status anytime and anywhere. The combination of semiconductor technology and biomedical makes biomedical chip arises at the historic moment, it not only provides the bridge between patients and medical personnel, and greatly improve the portability and accuracy of medical equipment, for the wearable medical equipment to provide excellent solutions.The general requirement of the Electrocardiogram(ECG) Analog Front-End(AFE) is discussed by analyzing the characteristics of ECG and the collection environment. Then, a low-noise, low-consumption, high input-impedance and adjustable gain Electrocardiogram AFE circuit is proposed after researching the optimal designing scheme. The circuit consists of a pre-amplifier, adjustable gain stage, a second-generation current transmission structure of low-pass filter, a Right-Leg-Drive circuit, a lead off detection circuit, etc. The core modules, designed in SMIC 0.18 μm process, power supply voltage of 1.2 V, it is based on capacitive coupling-AC feedback structure of preamplifier and obtained the good effect of common-mode rejection, adopted at the same time fully differential operational amplifier inverter input structure, while ensuring low noise and low power consumption under the precondition of realizing the collection of ECG signal and amplify, preamplifier consumption current is only 400 n A, the simulation results show that the frequency range of the input reference noise only 2.42 μV, on this thesis, the capacitance in the preamplifier circuits positive feedback is added, greatly improving the input impedance, compared to before adding the positive feedback by about 100 times, reaching 2.4 GΩ, improving the acquisition signal strength, according to the ECG signal frequency range, the design range of 0.5-150 Hz bandwidth, which can effectively inhibit out-of-band noise, at the same time the circuit gain is designed to be adjustable, in order to meet the chip’s ability to adapt to different acquisition environment, Right Leg Drive circuit to effectively suppress the common mode noise, improves the common mode rejection ratio, lead off detection circuit is used to real-time monitor the connection status, the chip power consumption current is 70μA, the chip area of only 0.35mm2, compared with traditional chip reduced about 30%, the performance meet the demands of ECG signal acquisition parameters.