Design Of Analog-front-end For MHealth Monitoring System

With the recent increasing popularity of wireless smart devices and wearable technologies throughout society,the mHealth applications have been growing steadily over the last few years.It is anticipated that launches of wireless fifth generation（5G）communications,engineered to greatly increase the speed and responsiveness of wireless networks,would bring new opportunities to mHealth.The current mHealth applications typically utilize mobile devices equipped with wearable sensors in collecting health data and physiological signals,such as Electrocardiogram（ECG）and electroencephalogram（EEG）.As the core part of the electrophysiological signal acquisition system,the readout front-end circuit（also known as the analog front end）has been one of the hotspots in the field of ICs design.The key challenge in designing biomedical ICs is the pursuit of low frequency,low noise,and low power,and thus,there is a trade off between noise,power,area and bandwidth.The main work of this paper is to study and design the electrophysiological signal acquisition front end circuit for mHealth monitoring system.Firstly,the basic characteristics of electrophysiological signals and bioelectrodes are studied.Based on these,the noise and interference sources in the acquisition process and typical front-end acquisition circuits are introduced.Then,low-noise and low-power circuit design techniques are researched,including a comparative analysis of low noise circuit design techniques such as auto-zeroing techniques and chopping modulation techniques,and an introduction to the characteristics of MOSFET operating in subthreshold region.Finally,the application requirements of the system,the electrophysiological signal acquisition circuit architecture and the design of each core circuit module are studied in detail.And the significant technical difficulties such as low noise,low power consumption and high input impedance are resolved.According to above analyses,the architecture of the front-end circuit is determined.This front-end circuit is based on a capacitively coupled chopper-modulated instrumentation amplifier（CCIA）.In order to reduce the power consumption,the supply voltage is scaled to 0.8V,and all analog circuits are biased in the sub-threshold region.The chopper-stabilized technique is introduced to eliminate the 1/f noise,and a dc-servo loop is employed in the CCIA to suppress the electrode offset.The whole IC realized in 40nm CMOS technology,and the whole chip size is 0.2mm².Simulation results show that it occupies 33.96dB gain at 0.8V supply,and achieves a bandwidth of 0.2⁸00Hz,a input-referred noise of1.97μV_rms,and an input impedance of 500MΩ@10Hz.The CMRR of this front-end circuit is 90.6dB,the power consumption of it is only 560nW,resulting in a noise efficiency factor（NEF）of 2.24.