Design And Implementation Of Digital Filter In High Precision ∑-ΔAADC In Gyro System

This paper researched the realization and testing of digital decimation filter circuit in Δ-Σ ADC. In this paper, the content’s subject background is high precision Sigma-Delta ADC in gyro system application. In gyro system, ADC is responsible for transferring the analog signal into digital discrete signal, the accuracy of ADC play a crucial role in gyro system, and the digital decimation filter is an important part of the Sigma-Delta ADC. Therefore, the design of high precision and low-power digital decimation filter is significant.In this paper, the CIC filter has been reduced the operating frequency of the differential circuit and power consumption. And the number of registers in the differential circuit is greatly reduced, also the area is reduced. In the traditional 128 down-sampling ratio filter design, usually three cascaded filter structure is used. In this work, a structure of non-multiplier CIC compensation filter has been used. Compared with the traditional structure of the compensation filter, the area is reduced by one order of magnitude. However, the compensation filter does not meet the anti-aliasing effects, thus adding a half-band anti-aliasing filter after the compensation filter. The resources of half-band filter is only half of the original CIC compensation filter. Therefore, the proposed four cascaded 128 down-sampling filter has smaller area, and lower power consumption. Test results show that the structure has saved 10% of the chip area.In this paper, the signal bandwidth of the 128 down-sampling digital filter is 1KHz, pass-band ripple is 0.01 dB, stop-band attenuation is 100 dB, noise floor is-130 dB, and the bits of digital signal output is 24. This design has been simulated in matlab simulink toolbox, verilog HDL coded, DC synthesis, placed and routed by SOC Encounter, static timing analyzed by PT. The chip has been fabricated in the process of 0.35μm CMOS technology. In addition, the design also passed FPGA design verification, after logic testing, the ENOB has reached 19.6 bit.