Research Of Low Power For Noc Based On Mesh-of-Tree Topology

With the development of technology and constant improvement of the users’ needs, more and more components and modules have been integrated into one chip, the advances in technology have made the speed and performance of the processors greatly improved, so on-chip design has been gradually into how to design efficient on-chip communication mode to realize the further optimization of the whole system performance. Therefore, the Network-on-Chip emerged, which based on the interconnection networks largely used in parallel computers. NoCs typically use the message-passing communication model, and the processing cores attached to the network communicate by sending and receiving request and response messages, which provide more standard interface for the expansion of the network structure and module reuse and improve the overall performance.Although NoCs solve the problem of the traditional bus structure such as low communication efficiency and design complexity, its power consumption and network latency could not be ignored. For example, the network power consumption of the famous Raw chip developed by MIT accounted for 36% of the total power consumption, Intel produced the Tera-scale chip, its interconnected power consumption made up 40 percent of the whole power consumption, so the further optimal design of the power consumption of NoCs has become an important issue on network structure design, how to implement the low power consumption of NoCs has been the key issue in industry and academia. Meanwhile, the network latency is also an important parameter in network optimization design, along with the development of the manufacturing process and improvement of the speed of the processors, the speed of communication between will greatly affect the whole system performance.The power consumption of NoCs is affected by many factors, among them, the network topology, efficient routing algorithm and application mapping algorithm are the major concerns to be considered. Currently, Mesh is a main structure in NoC design, but the problems of the larger diameter, the limited bandwidth and the higher power consumption of Mesh will be more and more obvious as the number of cores increases. Compared with Mesh, Mesh-of-Tree is a more ideal structure to save resources and power consumption, which has smaller diameter and lower node degree. But some routers in Mesh-of-Tree structure bear heavy communication task, which means these routers will consume more power consumption and easily get blocked. The communication distance between network nodes will also greatly affect the power consumption and network latency, so how to design an effective mapping algorithm to make the communication distance between the nodes with more frequent communication smaller, is another important issue to design. However, the mapping solution generated by the existing application mapping algorithm is not ideal, this is mainly due to the mapping problem is a category of NP problem, how to get the mapping solution close to the optimal mapping solution efficiently without exhaust all possible solutions is an important aspect for evaluation of the performance of the algorithm. The parameter selection also have a big influence on the efficiency of the algorithm and the final mapping solution, if improper parameter is chosen, it is likely to fall into local optimum, then the effect of low power consumption is influenced.To solve the above problems, a simplified Mesh-of-Tree topology was proposed, which aimed at alleviating congestion, saving resources and reducing the power consumption. Based on the simplified Mesh-of-Tree, an efficient routing algorithm was designed which considered both the network load and the shortest path between cores, balancing the network load, reducing congestion, the network latency and power consumption which maintain the system performance. Based on the problem of the traditional application mapping algorithm such as premature phenomenon and the limited optional solutions, a mapping algorithm which considering premature phenomenon and expanding the solution space was suggested, when the premature phenomenon occurred, the strategy of escaping from local optimal was adopted and regenerate the solution space. In order to measure the performance and efficiency accurately, Gem5 was used in our experiment, which was a full system simulation platform, and the benchmark used was PARSEC. The experiment result shows the power consumption in network can be reduced 5.39%-23.3% and the reduction in network latency is 4.23%-17.28% by applying the proposed routing algorithm compared with traditional deterministic routing algorithm. The proposed mapping algorithm decreased the power consumption by 4.5%-28.9% and 9.9%-21% reduction in network latency compared with the random mapping algorithm.