The Hardware Design And Realization Of High Speed Digital IO Based On PXIe Bus

With the continued enhancement of electronic equipment,the complexity of design is also improved gradually,for the testing requirments of these equipments is higher,which promotes the development of automic test system. As an important test module,digital I/O automatic test system can be used as a source to send 0/1 data to test equipment,or collect 0/1 data for analysis from test equipment,and it has been widely used in many fields.Firstly, the issue discusses the reach background and significance, presents situation of development, and raises design specifications. Combined with the subject indicators, the issue uses Virtex-5 FPGA as the main chip to design hardware, and by using internal resources of FPGA and some peripheral chips, achieves the desired functions. Unlike other digital I/Os which for sale, the subject innovatively uses FPGA dynamic reconfiguration, cooperates programmable power chip, to come to the data-level switching function. This method does not use logic-level converter chip, thereby reducing the difficulty of hardware design, providing convenience for developers.Then, the issue introduces the way of circuit design for detail, including the FPGA configuration circuit, the memory circuit, PXIe unit circuit and FPGA decoupling networks. Modules using online debugging and MASTER BPI_UP configuration modes, according to the debugging requirements, through the mode selection switch circuit to select. When design memory circuit, according to the requirements of high-speed memory chip on signal quality, the subject designs match circuit to improve signal quality which used for the address bus, control command signal lines and clock differential signal line, and to confirmate the matching circuit by simulation results. Further, since the Rocket IO transceivers require a lower power noise, subject designs power supply filter network which similar to the low-pass filter, magnetic beads have lager impedance for high frequency current, so it can filter out high frequency power noise. All power pins of FPGA have ripple requirments, while uncertainty has led to FPGA features can not accurately estimate the transient current. Therefore, the paper uses "Estimate- Calculation- Simulation- Fixed" approach, using simulation curve, repeatedly adjust the decoupling capacitor combination and capacitance values, for optimal FPGA decoupling network.PCB design is the most important part of subject. Paper starts with high-speed PCB design definition and process, giving expression to the importance of signal integrity simulation in PCB design. Then according to the design flow, respectively PCB digital I/O modules stratified, placement and routing. Phase wiring for highspeed DDR2 SDRAM memory chips were specifically designed, including reflection simulation, crosstalk simulation and timing simulation, access for some rules for PCB routing. In addition, according to the characteristics of the synchronization signal source for deriving maximum DDR2 SDRAM establish the time allowance formula and maximum hold time margin formula, combined with the timing simulation and timing chip manual provided, access for DDR2 SDRAM maximum line length constraint. For alignment rules PXIe bus, according PXIe specification, focusing on the alignment method are discussed.Last,using VHDCI-68 cable and SMA cabel to connect high-speed digital I/O module with NI-6544 which to test digital I/O. Controlled by PC program, digital I/O module and NI-6544 respectively send and receive datas, in the total process, change the data rate and data-level. Then compared with the data, prove that the digital I/O module function is normal, completing the index design.