The Research And Imlepmentation Of FPGA Static Timing Analysis

As the electronic information industry becomes a pillar industry in national economy, the integrated circuit(IC)industry has been supportted and developped vigorously. Field programmable logic arrays(FPGA), as a general-purpose chip, has been widely used in communications, aerospace and even national defense technology. To research and develop FPGA Independently is becoming urgent priority. FPGA’s static timing analysis(STA), which determines the operating frequency and reliability of the design of the chip, has become a necessary part of the development process.The basic principle and structure of FPGA is introduced in the paper. The paper do a in-depth research on the basic flow of FPGA software design in which static timing analysis plays an important role.The paper analyzes the types and characteristics of timing analysis.Static timing analysis is not concerned with the function of designs of the circuit and input stimulus,which is compared to dynamic timing analysis and statistical static timing analysis.Static timing analysis has the advantage of running faster and less computer memory,which is especially for the timing verification of large-scale circuits. Static timing analysis is a main timing analysis method in the integrated circuit.Timing constraints as a necessary part of static timing analysis provides the constraints window for users.Users can set timing constraints on circuit designs by the timing constraints commands.Three kinds of timing constraints commands,include clock timing constraints,IO timing constraints and Exception timing constraints,are designed in the paper for FPGA chips.The paper describes and analyzes the models of the timing constraints commands.Establishing timing library, which has a immediate impact on the results of static timing analysis, is the main content in the paper. In the paper, the timing modeling process is divided into unit and interconnection modeling process. Latency data in unit mode is measured by two measurement points. In the interconnection modeling progress, polynomial model is builded by the different kinds of interconnection mode.The static timing analysis software platform which is designed in this paper can meet the basic requirements of FPGA design with the correct timing analysis reports. Under the same conditions of test vectors, compared with the Xilinx ISE, the slack values in the static timing analysis reports is in the same level(ns), which has a certain practicality and reliability, and the software has been used in commercial fields.