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Worst-Case Performance Analysis And Design Of The NoC

Posted on:2017-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:J X WangFull Text:PDF
GTID:2308330488495455Subject:Integrated circuit engineering
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The development of the technology of NoC(network on chip) will promote the development of industry. Performance analysis has been a hot issue in research of NoC. Compared with the extensive research of average performance, the worst case performance analysis which will provide a performance guarantee in design of NoC has got more attention, using network calculus to evaluate the performance boundary of NoC is also a hot topic of in academic. This thesis uses network calculus in multi-path routing model platform which based on node split routing algorithm, aiming at optimize the performance parameter of delay bound and backlog bound, one of the problems is how to optimize the cutting point of contention model, the other is how to build an effective network monitor, and adjust the split path of flows at run time. These problems will be given a detailed description in subsequent sections. The main research points including the following aspects:(1) Network calculus analysis optimization modelThe article research is based on Fidler algorithm of the model, the algorithm model combines traffic characteristic parameters r and burst average rate b, service parameters service rate R and service latency T. Target traffic is treat as the research object, by removing, cutting, simplifying and other steps to obtain equivalent service curve stream object, and further delays to obtain upper and lower bound on the backlog in the worst conditions. But there is a problem the results accuracy of model calculation is not high. Network calculus is used to deduce delay bound in existing works, by means of cutting, simplifying and other steps to get the equivalent service curve of target flow, and further get delay bound and backlog bound in worst case. But the problem of the model is that the calculated results are not accurate enough, and there is a gap between the simulation results and the analytical results. In this paper, we aim at optimizing the selection of the cutting points in cross conflict model, determine the judgement of the cut-point selection by deriving the formula. Optimization algorithms and the original algorithm by experimental comparison of the differences in delay upper bound, the average optimization about 10%. Experimental results show that compared to existing algorithms, the optimized algorithm can optimize delay bound by 10% on average.(2) The dynamic contention matrixTo balance loads of NoC, Contention matrix is used to calculate the node splitting parameter, and to guide target flow multiple paths splitting in order to balance load and reduce network congestion. But the problems is the configuration process is static, the value is set only when the system is reset, once the contention of network flow changes, unable to cope with static configuration process. Static configuration process can’t cope with the situation when the contention of network changes. The article put forward the design scheme of dynamic conflict matrix, which can be real-time path adjustment, which can adjust the paths of flows at runtime, and reduce the network congestion. The average and maximum delay can be optimized by 30%.(3) Wormhole routing simulation platformTraffic analysis platform configuration uses a leaky bucket model contract, in order to be able to do simulation and analysis platform comparison experiments under the same experimental environment, wormhole routing based simulation platform is built. The platform use flits the basic data transmission unit, use contention matrix to compute node split to compute the parameter of node splitting, offline configuration node split than information. Configure the parameter of node splitting offline. The basic design unit of Network on chip simulation platform model is routing node, the node contains decoder, arbiter, input state machine, cross switch and other design modules.
Keywords/Search Tags:Network On Chip, Performance Analysis, Multi Path Routing, The Dynamic Contention Matrix
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