Parallel Optimization And Realization Of HEVC Decoder Based On Multi-Core Processors

With the continuous development of mobile Internet and multimedia, real-time hd video communication is becoming more and more widely attention. The high efficiency video coding (HEVC) standard was finalized in January 2013 by the Joint Collaborative Team on Video Coding (JCT-VC) as joint effort between ITU-T and ISO/IEC 55 HEVC standard can reach the same subjective video quality as its predecessor H.264/AVC at about a half bitrate , the network bandwidth reduced by half, so widely attention, However, the complexity growth of HEVC has become an inevitable obstacle for the real-time HD HEVC video decoding under the limited capacity of existing mobile devices. Due to energy constraints, more and more portable electronic devices adopt the low-power-consuming multicore processors based on ARM architecture the continuous growth of video resolution brings much greater pressure on decoding, making the efficient HEVC decoding solution on general processors a real challengeFirst of all, this thesis studied and analyzed the latest HEVC codec standard improvements compared to h.264, summarizes the decoder new features, research the latest ARM multi-core architecture processor (Big.LITTLE) architecture and features, analysis of the structure characteristics of parallel computing. Then, analysis of pixel reconstruction (Intra prediction, inter prediction, inverse quantization and inverse transform) coupling process data, the research is suitable for big, LITTLE processor architecture system of parallel granularity, this thesis selects the overlapping wavefront reconstruction scheme of parallel algorithms for pixels in CTB behavior basic parallel granularity. Secondly, study the HEVC codec coupling in the process of the loop filter data, respectively studies to the deblocking filter(DBF) and sample adaptive offset filter(SAO). This method performs the parallel vertical edge filtering and parallel horizontal edge filtering in separate passes to fulfill the dependencies of DBF, Sample adaptive compensation parallel computing in CTB line to basic granularity parallel. In order to improve the cache hit ratio and thread online rate, CTB column to deblocking filtering and sample adaptive offset is fused to a parallel tasks.HEVC decoder of this thesis through design and the implementation of the parallel optimization, the hd (1280 x 720) and standard definition (832 x 480), two kinds of test study column has realized the real-time decoding, the decoding frame rate relative to the serial decoder has obviously improved.