Study On Optimization Design Of CMOS Terahertz Detector

Terahertz technology is considered to be one of the future’s top ten technologies which can change the world. It has important applications prospects in many fields such as broadband communications, THz radar, medical imaging and security inspection. The development of low cost terahertz detector based on CMOS process is an important way to achieve practical terahertz technology in future.This dissertation combining research status, based on the structure of transistor, analyses the key parameters of transistor which effect terahertz response. Then we design two new CMOS THz detector and manufacture these detectors with electrical antenna by 0.18μm IC process and test those THz performance. We achieve high voltage response (Rv) and low noise equivalent power (NEP) without increasing the manufacturing costs. We find a new way for achieving a higher response of terahertz detector on chip. Based on the highly integrated advantages of CMOS technology, we design on-chip amplifier and driver circuit to achieve the first stage amplification of readout signal. The main results include two aspects:1. We design non-self-aligned structure and annular-gate structure of optimized FET by TCAD simulation tools. Then we manufacture these detectors with matched electrical antenna by 0.18μm CMOS standard process. Experimental results show the use of these two structures can significantly improve THz response of FET detectors. Non-self-aligned structure achieve 156% improving of Rv and 69.2% decrease of NEP compared to symmetrical structure. And annular gate structure achieve 100% improving of Rv and 42% decrease of NEP than conventional structure.2. Folded cascode low noise amplifier is designed for CMOS THz detector with bandwidth of 17 kHz, the open-loop gain of 69.8dB, the phase margin of 60 degrees. Then we design,a LDO current structure which can provide drive current within 10μA for CMOS detector.