Reseach On Reliability Of Copper Interconnnects In Integrated Circuits

With the rapid development of IC interconnect technology,the dimension of devices and interconnects are getting smaller and smaller, even the feature size reaches technology nodes with tens of nanometers. While the interconnection processing technology constantly get over its own shortcomings to meet the growing requirements of IC interconnect processing. However, some poor physical properties of copper and low-k materials, such as the strong diffusion of copper ions in dielectric materials and the low breakdown resistance of low-k materials, make interconnect reliability more deteriorating, so as to cause a "bottleneck" of interconnect technology. People has been studying the reliability problems of metals and dielectrics for many years, and various theories have been put forward, but some reliability problems that related with interconnect geometry variation and signal frequency rarely cause people’s attention. For example, the impact of some reliability factors, such as the skin effect, line edge roughness(LER) and misaligned vias, become increasingly apparent under the circumstances like increasing signal frequency and shrinking feature sizes, and so that the high-frequency signal model cannot be replaced by a DC model, lines with rough edges cannot be replaced with lines with smooth edges and vias cannot be regarded as a point that connects the upper and lower metal wires. For these reasons, this thesis is committed to do analysis and research on the effect of skin effect, line edge roughness and misaligned vias on the interconnect reliability.Firstly, by establishing a high-frequency current density model, this thesis studies the effective current density and temperature distribution of metal lines and the local electric field distribution in dielectrics, and furthermore, the relational models of current frequency and electromigration, stress migration and TDDB lifetime are obtained. Based on research results of some researchers and this thesis, we propose a new high frequency MTF model for metal and dielectric.Secondly, based on the effective resistivity model and interconnect temperature distribution model of LER, the temperature distribution of interconnects under different LER conditions are obtained, also the average lifetime of stress migration at vias are presented. In addition, with statistical theories and finite element simulation, the current and field distribution of interconnects with LER are modeled, and the average life expectancies for electromigration and TDDB under LER are obtained.Finally, a finite element simulation model of misaligned vias are created to do analyses and studies about the effect of misaligned vias on the average current density and stress of interconnect vias and the local electric field between vias and lines, and by numerical simulation method, the effect of misaligned vias on the reliability of metals and dielectrics are discussed.The results indicate that ignoring the effect of high-frequency signal and interconnect geometry variation will result in an over optimistic or over pessimistic estimation of interconnect lifetime, which leads to errors in chip-level lifetime assessment. Therefore, at the nanoscale interconnection technology node, it is necessary to consider the impact of interconnect geometry variation and high-frequency current, in order to establish a more accurate assessment of the interconnect lifetime.