Thermal deformation of electronic packages and packaging effect on reliability for copper/low-k interconnect structures

In the semiconductor industry, thermo-mechanical reliability has been a critical issue for both packaging and wafer level structures. Thermal deformations and thermal stresses are directly related to the packaging and wafer level reliabilities. This study addressed the above issues and contained three major objectives.; The first objective was to study thermal deformations of electronic packages, mainly by use of an experimental technique, high resolution moire interferometry. Different types of packages including a 3M CueBGA package, a Philips on board flip-chip package and a Motorola experimental flip-chip package without board were investigated. Moire results showed that thermal deformations of these packages were quite different from each other, leading to very different reliability problems in these packages.; The second objective was to study thermal stresses of wafer level Cu interconnect structures by semi-analytical approach and finite element analysis. In this study, a semi-analytical solution for predicting Cu line stresses was developed and verified with finite element analysis and x-ray measurement. Finite element analysis was employed to study the barrier thickness effect on Cu line stress. A simulation approach based on element birth and death technique was developed to simulate the whole wafer processing procedure in order to study the residual stress induced from wafer processing. Simulation results showed that large residual stress can be induced from wafer processing, which can significantly affect the wafer level structure's reliability.; The third objective focused on the chip-packaging interaction that has become a critical issue for packaging of Cu/low k chips. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips. This study involved thermomechanics analysis for both packaging and wafer level structures and was carried out using experimental measurements and finite element analysis. A simulation approach based on multilevel sub-modeling technique in combination with high resolution moire interferometry was employed to study this packaging effect. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures were deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures in order to assess the effect of ILD on packaging reliability. Results indicated that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures.