The Design Of Five-Stage Pipeline CPU Based On ORBIS32 Instruction Set

Recently, the amount of the researches on CPU is increasing in domestic. Also, there are many open source CPU architecture and CPU products in research field. The main idea of this paper is to design a self-control CPU which is based on the open source CPU architecture. The advantages of doing this are, firstly, the instruction set and the tool chain are used by most people, secondly, according to our own needs to design of self-control CPU.The design begins with the CPU instruction set. The rule of ORBIS32 instruction set is studied. According to the rules, the decode module of the CPU is designed, and the control signal and operand address is decoded. At the same time, a lot of lead optimization has been done for branch jump, ALU calculation, LSU access in the decode module. The ALU module has also been redesigned. The ALU function module is divided into several sub modules for future ASIC replacement. In the design of write back signal, the TAG signal is designed to control the procession of pausing signal. In the Memory access module, memory access line is designed for CPU memory access.We made a concrete analysis of several key problems in the process of CPU design on the basis of the experimental results, the problem of the data correlation and the must suspension pipelined and branch jump is solved perfectly. The validity of the problem is proved by assembler programming. Through the design of write back data TAG, pipeline stall could be controlled for the multiplication calculation, the memory access phase, and the other operations that cannot be obtained at the execution stage.Finally, a software test method is used to design for CPU which can be tested. The self-testing assembly set is designed to be a test drive and reference model. The detector is designed to detect the final results. Through experimental testing, the test of CPU design has been completed and the function of CPU has been verified.