Design And Formal Verification Of PCL Based On SoC

Nowadays, as the integration of SoC chips becomes higher and higher, there aremuch more chip pins to be needed. The limited pins should be utilized reasonably andfully. In addition, with the number of the pins increasing quickly for the SoC chip, thetestability of the circuits and systems are sharply declining. The boundary scan testtechnology can improve the testability of chips and it will never influence the module·swork. In this paper, the pad control logic module has been designed to resolve thereuse of the pins and improve the testability.The verification process for PCL is one of the most important parts in this thesis.Since formal verification does not need the test bench and the test case, it will reducethe cost of verification and will enhance the speed of the verification for the SoC chip.By using the OneSpin tool, PCL module is verified based on the property check theoryand the result is that the design matches the design specification.