Design Of Clock And Reset System With Low Power Consumption For Multicore DSP

As the heart and neuro of the DSP chip, the clock and reset system poses a direct influence on the property, power consumption, normal start and reset from abnormity of the chip. Meanwhile, the low-power design has already become an important issue which shall be taken into account in the process of chip design. The clock and reset system is closely related to the techniques of low-power design, many of which, in turn, need to be supported by the clock and reset system. However, the designing of the clock and reset system may also involve some low-power properties. Through combining the actual demand of a multicore DSP processor independently researched and developed by our university, this paper has designed a multicore DSP clock and reset system which supports the control of system-level low power consumption. Therefore, the main duties and contributions of this paper are as follows:By combining the system structure and operating features of the target chip, the paper has constructed a basic structure of clock system and reset system for the chip and completed its function design and support for power management design.The paper has conducted a selective analysis and design on the difficult issues involved in the design of the clock and reset system, designed frequency dividing circuits with equal duty ratio, analyzed and designed a solution for processing the reliable crossing clock domain of the clock system, established an exclusive circuit where clock switch can be carried out without burrs between any two clocks and realized the dynamic allocation of crossing clock domain for the clock and control system by using the shadow register.The paper has accomplished the coexistence of multiple clocks for the target chip, established a complex clock system which can realize the dynamic allocation, frequency division, aligning as needed and clock switch without burrs and implemented a multi-level and multi-mode system reset logic.This paper has also conducted verification on the design with a variety of means. A relatively comprehensive functional verification has been carried out on the module level and system level, verification has been perfected on the basis of fraction of coverage, and reinforcement has been conducted with a formal method. From the results, it can be concluded that this design has reached the expected design objective both on the aspects of functionality and performance and can practically meet the requirements of the target chip.