Design Of Loop Buffer Circuit Module For Application In A Low Power DSP Processor

In this thesis, loop buffer for a low power DSP processor is designed. This DSP processor takes advantage of the characteristic of frequent repetitions for loop operation in the signal programs, a special hardware module for handling the repetition is designed to eliminate the stall of pipeline caused by fetching the loop instructions in this DSP architecture. And the power of fetching the instructions is decreased since the loop is handled with zero over-head.Loop processing technology is described in the thesis, and related research of zero over-head loop and loop buffer is carried out in the DSP processor.Firstly, in aspect of function of loop buffer, based on zero over-head loop unit, the loop buffer function, the loop buffer supporting loop body and response to disruption of the branch are respectively designed.Secondly, in aspect of structure of loop buffer, the loop buffer is divided into control module and storage module. In the control module, three control submodules are designed which is conducive to allocate hardware resources and reduce hardware over-head. When storage distribution module is designed, the state machine is used, this method not only can cover all loop conditions, but also reduce the complexity of logic design.Then, it is studied the verification method for simulation verification and power analysis of loop buffer to ensure that the loop buffer can store and distribute the loop instructions correctly.Lastly, the power of loop buffer is analyzed, the results show that the power of fetch path and clock power when the instructions memory L1is idle are reduced. Meanwhile, based on a65nm technology, logic synthetize is conducted for the loop buffer. Its frequency of operation is up to600MHz, the dynamic power is6.67mW and the cell leakage is0.53mW.The jump of loop is operated in a separated module without stall of pipeline and the DSP performance is improved.