Research On Some Key Techniques Of Network-on-Chip

With the development of intergrated circuits and application requirements of market, more and more Intellectual Property cores can be intergrated on a single chip. The shortcomings of traditional Bus-based architecture in network scalability, bandwidth, latency, power consumption and global synchronization have been exposed gradually, which is hard to fill the communication requirements of complex System on Chip. Network on Chip can overcome these shortcomings by appling distributed communication mode, which is deemed as the promising solution for communication of complex System on Chip. The urgent research project to be realized in Syetem on Chip is the way to make efficient communication between IP cores. In this paper, the research we did focus on the topological structure and routing algorithm of Network-on-Chip, subnet dividing and the communication architecture of wireless Network-on-Chip. The main contribution and conclution in this paper can be concluded as follows:1. Topology design of Network on Chip. In this part, we first propose a hybrid connection-based Mesh topology, in which we combine Mesh with a bus-based architecture. Packet routes on Mesh topology when the routing path is not congested; otherwise, it routes through the bus-based channel to the destination in one hop. The simulation results show this hybrid topology can efficiently relieve the degradation of network performance cosed by network congestion.2. Routing algorithm design of Network on Chip. In this section, we propose a Hybrid Pseudo Adaptive router algorithm. When the network is not or less congested, packets are routed along the prespecified path; when the prespecified path is congested, the router will choose the next hop according to the congestion degree; when all routing path in Mesh topology is congested, the packet is transmitted through the scharing channel. The evaluation results show the improvements in network performance with comparison of Dimension-Orderd, O1TURN, DyXY routing algorithm. 3. Subnet divides of Network on Chip. We first proposed a subnet dividing algorithm based on exhaust searching, thus to find the minimum traffic load between a subset and other node of the network. Simulation results show this algorithm can efficiently reduce the traffic between subnets and relieve the requirements of wireless bandwidth.4. Communication architecture design of wireless Network-on-Chip. In this paper, we first proposed a scalable connection-based Time Division Multiple Access architecture for wireless NoC. A central arbiter is introduced in order to control the communication between subnets, thus to make fully use of the limited bandwidth resources. Furthermore, network congestion can be efficiently relieved by appling single-hop instead of multi-hops communication in this architecture. The evaluation results show the great improvements in network throughput, average latency and energy consumption with comparison to the WCube architecture. Moreover, we carefully design a central arbiter. Demonstration shows that the controller is easy for scalability.