An Accelerated Ray Tracing Algorithm For The Intel（?） Xeon PHI^TM Architectures

Ray With the development of multimedia technology and CG technology, rendering engine has become more and more widely used in film animation, simulation and game effects. There is no exception that Mainstream renderers always attach great importance to raytracing which play an important role in rendering system. Ray tracing can generate real global illumination effect, thus it is widely used in highly realistic rendering. However, this algorithm is computationally intensive causing the poor performance on mainline CPUs, which turns into the bottleneck of realistic rendering. This disadvantage increases the cost of film and television production, at the same time also limits the more widely used of ray tracing algorithm. Therefore, it is worth researching the acceleration of ray tracing.There are many Remarkable achievements on ray tracing optimization for GPU. In recent years, Intel proposed the Xeon phi coprocessor which is based on many Integrated Core architecture-Intel Many Integrated Core (MIC), Its flexible architecture provides a good platform for the research of ray tracing acceleration. This architecture has many cores and per core has one VPU(Vector Processing Unit) with 512 bit. With all these features above and easy to programming the MIC architecture is suitable for the parallel acceleration algorithm in the field of rendering.To improve the low speed of ray tracing in photorealistic rendering resulted from the large quantity of ray-box intersection tests, a novel algorithm based on Intel Many Integrated Cores (MIC) for parallel ray tracing is presented in this paper. In the stage of scene preprocessing, this algorithm constructs a bounding volume hierarchy (BVH) with a branching factor of 4 which adapts to the architecture of MIC. Afterwards, the whole process of ray tracing is controlled by CPU. It adopts the optimized multi-threads scheduling strategy to schedule the coprocessor MIC to conduct ray-box intersection tests. In the meantime, asynchronous data transmission between CPU and MIC is achieved and the computing power of both CPU and coprocessor is well exploited and utilized in this stage. Furthermore, in order to accelerate ray-box intersection tests, we propose a parallel intersection algorithm which takes full advantage of MIC’s wide SIMD processing unit and applies vectorization operations on the implementation of intersection between ray and four boxes at the same time. The experimental results show that, compared with the CPU native mode, the algorithm presented in this paper is 2～4 times faster in the ray-box intersection test, ending up with a well accelerated ray tracing rendering process.The area light in rendering engine is aimed at more realistic illuminance effect. Always it should take a large number of samples across light surface to get a better effect. This process will call ray tracing core to track shadow rays repeatedly which will need large amount of calculation. This paper implements a rapider area light with sobol sequence and monte carlo integration.