| As the feature size narrows, yield loss caused by design has become a choke point when integrated circuit developing in the light of Moore’s law. Design and manufacture cannot be isolated from each other any longer, and information interaction becomes ever more important. That’s why the technology of design for manufacture (DFM) appears. Dummy metal insertion technology, which uses dummy features to control pattern densities of interconnect layers, is a widely used method of DFM to optimize chip flatness after chemical. mechanical polishing (CMP).However, filling dummy metals introduces some problems. On one hand, parasitic parameters of dummy metals influence timing and power, decreasing chip performance. On the other hand, the exposure wavelength is on the brink of the theoretical limit of the lithography system. That means exist of dummy metals can further deteriorate litho distortion, requiring more attention.Based on the fact, this paper proposes a litho-friendly dummy metal insertion process to achieve balance between litho effect and chip flatness. The main contributions are 1) studying the influence of pattern positions on the lithography distortion based on line and line-end location models,2) proposing an innovative pre-fill strategy that can repair the existing T-shaped, Z-shaped and line-end lithography hotspots, and 3) designing a flexible and efficient litho-friendly dummy metal insertion process to further reduce new lithography hotspots.An experiment on the OR1200 benchmark circuit in 45-nm technology reveals that after the litho-friendly dummy metal insertion process,41.47% of the particular original litho hotspots has been repaired. At the same time, the number of newborn hotspots decreases by 70.71% compared with ordinary insertion process. The fix rate of MWC hotspots reaches to 86.67%. The number of new LEC hotspots gets a four-fold reduction. Finally, the new litho-friendly insertion process reduces filling volume by 1.62% without deteriorating flatness. |
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