Litho Defects Research In ASIC Layout Design

According to Moore's law, IC is fast developing, and the current mass production technology has entered 65nm node. Along with the continuous decrease of characteristic dimensions (CD), the litho size has already approached to the current exposure system's (using 193nmArF excimer laser stepping scanning exposure machine) theoretical limit. This situation causes serious image distortions after litho on silicon, including line-ending, necking and corner passivation, and so on. And the distortions seriously affect the quality of circuit, decreasing the yield and stretching the production cycle. Currently, the traditional solution is resolution enhancement technology (RET), including optical proximity correction (OPC), phase shift mask (PSM), and double patterning technology (DPT), and so on.Based on ASIC layout design, this thesis considers and solves the litho variation problems in layout back-end design, to enhance the yield and short the production cycle. This paper analyzed the cause of litho defects from the exposure system in the background of the development of IC. In the experimental process, firstly we complete the layout design flow, including Synthesis, Floorplan, Placement, CTS (clock tree synthesis) and Route. And we use the Cadence software Inshape to make litho simulation with the layout of circuit after routing, acquiring the litho hotspots.Then, we classify the hotspots, and summarize the types of routing, using this to guide the EDA tool to avoid the hotspot routing types.Meanwhile, we use Cadence software Chip Optimizer to modify and remove the hotspots in layout, under the guidelines of InShape.Experiments show that the solution which embeds in the chip back-end design flow can run with some back-end validation work, and will not increase mass design times.After the hotspots modification, the number of hotspots is significantly reduced, and production cycle is shortened while yield increased.