Design And Implementation Of The Static Color Image Compression System Base On FPGA

Today’s society get into information age, the image play a important role in the process of information transmission, so about the image processing technology has become the focus of human reseach in the aviation, aerospace, biomedical, military and communication field.It was found how to storage and transmission the large image data during the study, already has become not be ignored the technical difficulties in the field of image processing. If blindly increase the storage space and transmission bandwidth can’t solve the problem fundamentally,then the only way is to compress the image data.In this paper,the main research is the principle of image compression and encoding process analysis,which fouces on the core algorithm.through discussion and compare of some classical algorithms,then find out the algorithm with the high compression ratio and suitable for processing hardware architecture, then it become the algorithms of the compression system after improvement, which is also the difficult point of this paper’s research contents.The main content of this article is a image of BMP format is compressed to JPG format according to the JPEG encoding standard. Through the logic chip FPGA and hardware description language Verilog HDL combination, complete hardware design and simulation on ModelSim of each module.Final after the compressed data accordance with standard JFIF file format handling, transfer to the PC, by the windows system decoding software to decode the final image. The core of the article is to study the algorithm of DCT transform in the course of JPEG compression, discussed different fast algorithms’ processing methods, to achieve the effect and the compression ratio,after analysis can obtain to use LLM-12 algorithm not only structure fit for hardware design technical indicators – area and speed,but also the compression effect and the compression ratio are relatively good,so this article on the selection of this algorithm processing.However, consideration the hardware design index requirements there are some drawbacks of this algorithm, so the text make appropriate improvement and optimization for the inadequacies of the algorithm. Mainly with reference the theoretical ideas of Bin-DCT algorithm, the float is expanded times base on need then interception the nearest integer as the original value, so FPGA only make additions and shift processing. By improving elimination of the multiplication,so that not only improve the speed but also reduces resource consumption of the chip.The quantized is going after DCT transform, the process by keeping the low-frequency signal with the large energy, lossing the high frequency signal with small energy to achieve compression. The hardware to do the divisions complex and slow, not meet the hardware structure design requirements. So the paper improved division of the quantization process after analysis and research the laws of quantitative, and ultimately hardware only make add and shift processing. After quantization is quantized coefficients encoded, the text use the standard Huffman encoding,by means of four standard Huffman table to complete the final process,the encoded data stream is the entire image information through compression processed.In the paper the entire hardware system by pipelined design, data processing is a combination way of parallel input and pipeline design, which not only shorten the wait time and data transfer time between modules, but reduce resource consumption of FPGA chip. The entire system development platform is based on Lattice’s FPGA chip of ECP3 series and the company’s Diamond design software. The paper using different fast algorithms for the same image to compression processed on the PC through software, and then analyzed compression result, the compression ratio is 30: 1 with improved LLM-12 algorithm, higher than the previous improvements LLM-12 algorithm. Although the compression ratio slightly lower than the LLM’s, the improved algorithm structure is more conducive to rapid processing of the hardware. In the functional design of hardware module, compiled and comprehensive to the improved algorithm or not, hardware resource consumption fell 7% from 9%, the speed is increased by 12 times。Final overall system compression ratio of 30.8: 1 after improved, the visual effect is good.