| As Internet user number expanded rapidly and abundant network applications continuously emerged, the current Internet infrastructure is confronting the following two obstacles. Firstly, the current link rate of core networks has reached as high as100Gbps,which requires routers to provide the matching fast forwarding capacity, secondly, network applications such as P2P,electrical commercial and on line stock exchange are continuously developing and maturing, it is the edge routers’obligation to do a series processing upon packets as encoding/decoding、traffic shaping and ordering. The current network processors based on general-purpose and multi-core CPU has become a hot issue among industry, it accompanies general-purpose and multi-core CPU with hardware acceleration engine of packet processing and implements high-speed forwarding ability and packet processing in depth. Multi-core and multi-thread processing could hide the access delay of DRAM in software and provides the demanding high programming flexibility in control panel, network acceleration engine could be utilized to implement fast path of packet processing by exploiting hardware speediness and parallelism. However, general-purpose and multi-core network processors are exposed to a drawback of relatively high I/O interaction delay between software and hardware, which imposes restrictions on the improvement of packet processing capacity. Facing with this problem this article proposes a novel network processor implementation model called Sandwich by making improvement of the original processing model and memory access model of general-purpose and multi-core network processors, the main effort and innovation includes:1. The constituting structure and characteristic of special-purpose CPU based and general-purpose CPU based network processors are intensively analyzed, and the different processing model and memory accessing model of both sides get compared, through which it gets clear where the bottleneck that limits the performance of general-purpose and multi-core network processors lies in. The proposed implementation model can best reduce communication costs between hardware and software in packet processing, and further relief the workload of software. The memory accessing model accelerates the CPU’s access speed to DRAM banks and implements flexible control panel by allowing storage of whole packets which CPU could processes deeply.2. The algorithm which maps the Fib lookup procedure into SandwichNP has been designed. In this algorithm, the whole lookup period is divided into three segments which is in sequence mapped into ingress acceleration, software processing and egress acceleration model in SandwichNP. The algorithm only requires at most one memory access for each packet lookup to complete and multi-thread processing can further hide the looking up delay. From the view of storage efficiency, the software and hardware cost extremely low amount of memory to store large-scale forwarding table of core routers and the storage will not expand dramatically even the table size grows rapidly3. The above Fib lookup algorithm is implemented in Galaxy NP-a SandwichNP prototype, and tests of multithread packets I/O and packets forwarding rate under real network circumstance has been carried out. The results show that the packets I/O and forwarding rate could stay the same in any parameter settings and both grow with link rate, multi-port lOGbps packet line rate forwarding could be guaranteed using SandwichNP.In summary, aiming at solving the problems that general purpose and multi-core network processor faces with, this article proposes a novel NP implementation model called Sandwich. This model has been successfully applied into the general purpose and multi-core NP which is constructed with indigenous CPU. The research has theoretic meaning and practical value to improve packet processing performance of general-purpose and multi-core NP. |
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