The Design And Implementation Of ATM Traffic Monitor And Analysis Probe Based On Network Processor

Data Network bears the weight of real time and multimedia operation more and more. ATM is widely used on backbone network for its dependable QoS. ATM traffic monitor is an important way for guarantying network performance and reliability. And ATM traffic monitor is very significative for ATM network operation and maintenance, troubleshooting, and traffic engineering.This paper analyses the process of ATM cell exchange in detail, proposes the ATM performance metrics. Based on Motorola C5 network processor, an ATM traffic monitor and analysis probe is designed and implemented in this paper. The probe captures and analyses ATM cells from ATM network link and provide performance metrics and statistical results. As an important part of ICT good-sized project "NetTurbo network traffic monitor and analysis system", the probe has been applied in actual network monitoring.The main achievements in this paper are described as follows:First, design of the ATM network performance metrics. Based on the analyzing ATM network hierarchy and protocol, ATM traffic performance metrics are classified into three levels: Port, VP, and VC. And the probe supports custom VPCs monitoring.Then, design and implement an algorithm for finding ATM cell boundaries in C5. After receiving a byte data stream consisting of 53-byte ATM cells, the RxSync programmable processor finds the cell boundaries by applying the Header Error Check (HEC) CRC sequentially to five-byte segments, checking the first four bytes against the fifth HEC byte. If the remainer of the five-byte multinomial divided by x~8+x~2+x+1 is 0, the five-byte is a correct cell header. With the later 48 bytes, an ATM cell is formed.And then, design and implement VP table and VC table lookup algorithm. In ATM cell header, the VP and VC employ 24bit in UNI interface, and employ 28bit in NNI interface. Lookup in 28bit table is very hard and will consume large memory space. A high- efficiency algorithm is proposed in this paper, in witch we compress VP and VC to 16 bit, and reduce time and space complication greatly. Table lookup is implemented in RxByte processor.Last, design and implement ATM traffic monitor and analysis probe based on C5 Network Processor. The probe supports traffic monitor and analysis in all ATM protocol- hierarchy. The hardware platform is standard CPCI 2.16 chassis, which support 6 monitoring card at most. Every monitoring card includes an OC-12 port and...