Model Absorption Current And Estimate Voltage Drop

With the chip design of integrated circuit(IC) stepping into nano-technology, power network design andanalysis become a key factor to restrict IC development. The problems arisen by power network design arelikely to cause circuit logic error, and further lead to a fatal problem that the chip can not implementfunction properly. Power network analysis technology not only provides efficient verification for thecorrectness of its design, but also lays a foundation for further optimization and guidance for furtherresearch.This thesis presents an absorption current model for circuit module in physical level, the estimationapproach of node voltage drop, and the optimization method of power network area. Under the premise ofvoltage drop constraints, the key idea aims at power network model. This thesis introduces the establishedcurrent model to construct modified nodal equations, uses the conjugate gradient method to solve the nodevoltage drop. Furthermore, a directional and selective incremental optimization method is proposed tosuccessfully optimize the power network area. The proposed method is tested by experiments onbenchmark circuits. The thesis is made up of following aspects:1. The current model of circuit module in physical level.Based on the input and output of circuit module, a top-down absorption current model is proposed, whichnot only combines the module area and switching activity, but also successfully introduces the randomfunction. The experimental results indicate that the proposed current model is more consistent with thecurrent distribution in actual chip, and the fluctuation of node voltage drop is smaller than previousmethods.2. The node voltage estimation method of power supply network.To the estimation of voltage drop, if the node voltage analysis is not sparse positive definite matrix, it doesnot show certain advantage in computation time and accuracy. This thesis presents an improved methodconsidering the supply pad as a node so that it can be introduced the MNA equations to generate thecorresponding matrix. Finally, the conjugate gradient method is used to solve the equation of the nodevoltage. The experimental results show the number reduction of iterations as well as save the computationtime.3. The power mesh topological optimization for multiple voltages SoC.This thesis proposes a directional and selective incremental optimization method. According to thecurrent distribution of power network and the location of maximum node voltage drop, there is a directionto increase the number of lines and multiple width adjustment of power supply line based on the originalpower network. The experimental results show that the proposed algorithm not only can optimize the powernetwork area, but also save CPU time...