Static And Dynamic Voltage Drop Analysis On SoC

With the continuous shrinking of process technology, higher frequency and lower supply voltage in SoC design, power density increases sharply. For the SoC design in 90nm and beyond, power consumption and voltage drop become very important parameters. In this trend, power integrity analysis is becoming a necessary task in signoff stage before chip tape-out. Moreover, static voltage drop analysis only is not enough to find and solve all the potential problems brought by large voltage drop. It is necessary to do dynamic voltage drop analysis, which is a more important and complex task. In this paper, we use an example of CPU design in CMOS090 technology to introduce the method of static and dynamic voltage drop analysis. In order to meet the requirement of 1GHz frequency in CPU, a supply voltage of 1.2V is chosen.