Verification And Physical Design For Signal Processing SoC Of Digital Sun Sensor

As one of the key components of satellite’s attitude control system, Sun sensors mainly consist of three parts, including optical head, image sensor and signal processing circuit. The system integration degree will be improved by using SoC technology on signal processing circuits, and this is conducive to the sun sensors towards the direction of miniaturization and low power consumption and high reliability, which make it more than satisfy the demand of satellite miniaturization development.The working principle of digital sun sensor and the basic structure of digital sun sensor’s signal processing SoC were introduced at first. The centroid algorithm including its hardware structure and software function were described in detail. Then the paper focused on functional verification and performance verification for signal processing SoC of digital sun sensor. As the centroid algorithm need hardware and software to work cooperatively at the same time, it used the method of hardware and software collaborative simulation to perform a more reasonable verification for the system’s global function. The main purpose was to judge whether the software and hardware would work correctly and cooperatively. Then it realized the system with XILINX FPGA and further verification for the system’s function and performance were performed with the method called FPGA prototype verification. Furthermore, the Margin of error was calculated. As a result, the calculation precision of the centroid algorithm can achieve the level of0.001°when there is no system error existing. However, the precision is about0.1°at the case of Z axis rotation error existing and0.2~0.4°at the case of X axis rotation error existing.At last, physical design with the SMIC90nm integrated circuit technology for the hardware of signal processing SoC was finished based on the flat design process. Given the narrow size effect on the chip performance, much attention has been paid on the timing convergence and signal integrity. What’s more, many measures have been taken on the design for yield. The size of the chip is4218μm×4143μm and the frequency of the system clock is200MHz. The power consumption is297.4mW.