Vector Processor Design For Parallelization Of Soft Baseband Terminal

Now, the4th Generation communication technology represented by LTE/LTE-A has come to its commercial stage, LTE-A evolves from LTE should provide higher throughput as well as be forward compatible with existing LTE standard. It shows the following two characteristics:1. Baseband processing computation density is increasing;2. protocol mode varies. So it brings higher demand for the terminal processor chip which is restrained by power and area. It is required to consider the performance and power as well as flexibility and upgrade cost together. Therefore, software defined radio baseband (soft baseband) technology as its high flexibility and low cost to upgrade gradually replaces the traditional ASIC design method, and becomes the trend of mobile terminal chip development.This thesis focuses on the core algorithms of communication systems which use Orthogonal Frequency Division Multiplexing (OFDM) and Multiple Input Multiple Output (MIMO) technology, including FIR filtering, FFT/IFFT, MIMO channel estimation and detection, Viterbi decoding and LDPC decoding, etc. The results show that these algorithms own large amount of computing as well as good parallelism, which provides feasibility of vector processor based soft baseband technology. Therefore, based on the analysis of these core algorithms from data flow and hardware implementation aspects, this thesis proposes parallel implementation scheme for them, and designs the vector processor model.The work of this thesis includes algorithm analysis, vector processor design, and performance verification.1. Algorithm analysis. By analyzing the characteristics of the algorithms, the parallel implementation scheme is proposed. FIR filtering, FFT/IFFT, Viterbi decoding, LDPC decoding algorithm adopt data parallelism within the algorithm. The key is to solve data alignment when accessing memory. To applying task parallelism in MIMO channel estimation and data detection, a soft output algorithm with good consistency is proposed.2. Vector processor model design. The structure of popular communication baseband processor is analyzed, including SODA (Signal-processing On-Demand Architecture), Ardbeg, AnySP and TI C64series. According to the parallel scheme of the core algorithm, a SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word) mixed structure vector processor model is proposed. First, the design parameters is analyzed including supported fixed point data word length, the width of SIMD and the ratio of each kind function unit. Then the details of the processor architecture are described, including arithmetic and logic unit, multiply unit, memory access unit, control and scalar unit, register file, etc. At last, the instruction set and the C compiler design method are given.3. Implementation and verification. The processor is modeled by LISA to get a cycle accurate model and assembly tool chain. C compiler is also designed for the processor. The Verilog generated by Processor Designer is synthesized in ISE and verified on ML605development board. Through comparison of FFT, FIR processing with TI C64processor, the performance has improved.