| With the continuous development of wireless communicationtechnologies, communication standards and protocols are frequentlyupdated to meet the demands for high-speed data transmission. Nowadays,with both powerful computation capabilities and high-degree flexibility,multi-core DSP has become one of the mainstream solutions for wirelesscommunication baseband processing. However, there is no benchmarkavailable for the performance evaluation of wireless baseband processor.Furthermore, it is demanded that the potential of multi-core DSP needs tobe further explored. In this thesis, DSP architecture targeted at wirelessbaseband processing will be studied, and the design of accelerator arrayunit will be proposed which can provide the basis of test and evaluationplatform for further study. The content of this thesis mainly consists of twoparts:Firstly, based on the analysis of the kernel algorithms commonly usedin wireless baseband systems, by selecting the typical applications, thethesis will design and implement a set of benchmark for performanceevaluation of multi-core processors targeted at wireless basebandprocessing. The thesis will also analyze the parallelism and computationcomplexity of the benchmark, and provide the performance of thebenchmark on x86platform as a reference.Secondly, the thesis will survey the existing solutions for wirelessbaseband processing, and summarize the characteristics of variousarchitectures and the trends of development. Referencing the existingarchitectures, this thesis will propose a hybrid architecture of multicore DSP and accelerator array based on the analysis of the proposedbenchmark, which is targeted at wireless baseband processing. This thesiswill focus on designing and implementing the VLIW architecture foraccelerator array unit and special instruction extension based on theanalysis of benchmark. The evaluation result will show that the proposedPE can basically satisfy the demand of wireless baseband processing. |
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