Research On Design For Testability Of Display Driver Integrated Circuits

Display driver chips have developed rapidly with the continuous advancement o f integrated circuit production technology.The gradually expanding scale of display driver chips possess more functions than ever before.The increasing complexity of the display driver chip structure not only puts forward higher requirements for chip design,but also brings more challenges to the final test of the chip.Nowadays,the continuously shortening iterative cycle of chip products in the consumer electronics market puts design-for-test(DFT)in an important position,as it requires higher qu ality,less cost and test time of chips.The main technique of DFT is to incorporate chip testing into the design specifications of the chip,and to enhance the testabilit y of the chip by adding some circuit structure that does not affect the normal func tion of the chip,thereby reducing the test cost.This article originated from an enterprise project,and formulated a testability d esign plan for the digital circuit part of a display driver chip and verified its feasib ility.This display driver chip is a high-performance chip dedicated to the display p anel of a mobile phone.It has more memories,faster chip running speed,and mor e complicated clock domains than the former display driver chips,which greatly im proves the DFT difficulty of the chip.The main techniques of integrated circuit DFT are studied in-depth,including s can insertion test method,boundary scan test method,logic built-in self-test method and memory built-in self-test method.By analyzing the advantages and disadvantage s and application scenarios of each design method,combined with the display drive r chip,it is determined to use the scan insertion test method to complete the testab ility design.Moreover,the basic test architecture for scan insertion test is studied.The flip-flop in the circuit is replaced by multiplexed flip-flop,linking all scan flip-flops to form a scan chain.Then the article analyzes the adverse effects and optimization m ethods of DFT,and implement the basic test mode of DFT in this display driver c hip.In order to achieve the test objectives of this display driver chip,the present s tudy inserts test points in the circuit to improve test coverage.The scan compressio n method is adopted to solve the problem of too long test time.Use the on-chip c lock for at-speed testing,which overcomes the problem of timing testing in high-sp eed circuits.Develop a scan shift grouping scheme,and complete a low-power testa bility design.This article completes the DFT of this display driver chip on UMC 55nm proc ess.Using Tetra MAX software generates test patterns and analyzes test coverage.B uilding a simulation verification platform and using test patterns for VCS simulation verify the effectiveness of the test patterns.The chip area is about 2.03×10~6 square microns,of which the additional DFT circuit accounts for 6.37%.The highest test coverage is 94.18%,the number of test patterns is 7540,and the average flip rate is 19.55%.The results reveal the effectiveness of the DFT structure in the chip,wi th improving test coverage,and greatly reducing the chip mass production test time.