A Study On The Modeling Of VDOMS Based On BSIM3v3

Power VDMOS device （Vertical Conduction Double-Diffused Metal Oxide Semiconductor）is one of the power electronic mainstream products. With its higher input impedance, wider safetyoperating area, faster switching speed and better thermal stability than other general powertransistors, VDMOS is used widely in the switching power supply, motor drive, energy saving light,automotive electronics, and so forth. in recent years, China has made progress in the research ofVDMOS power devices, but still it is not very mature, and a lot of the VDMOS products in Chinaneed to be imported from foreign country, so it has very important practical significance to theVDMOS device characteristics research, and the device modeling, also the model optimization.This paper selects and uses the VDMOS device, developed by one Semiconductor TechnologyCompany. On this paper briefly we introduces the application of VDMOS, its developmentprospects and significance of the VDMOS model research. An all-overview of the relevant modeltheories then is presented, including the SPICE model and its development, also the maincharacteristics of the BSIM3v3model and device physics mechanism BSIM3v3mainly considered.Next the device test system, modeling simulation software, the detailed and comprehensive modelextraction steps are introduced. The development of VDMOS structure then is described, The DCcharacteristics, the thermal temperature characteristics and the dynamic capacitance characteristicsof power VDMOS device are analyzed. Finally, the DC test and dynamic capacitance test onVDMOS are done, including the output curve, the transfer characteristic curve and the capacitancecurve with the bias voltage variation, the VDMOS model is created with some special simulationsoftware. In the process of modeling, it is found that the initial BSIM3v3model can not characterizeVDMOS well, because it is mainly oriented to low voltage and low power MOSFET device.Therefore, based on the BSIM3v3model, the sub-circuit model is proposed, adding a resistance inthe drain controlled by the gate voltage and drain voltage, to well fit the VDMOS test data, and toimprove the VDMOS model accuracy. At the same time this paper makes some changes to theVerilog-A model file of the BSIM3v3, modifying the original equation code with in Verilog-A,adding several parameters mainly used to fit the linear region and saturation region of the IV curve.The simulation curve with the optimized BSIM3v3model shows that it is consistent with the actualVDMOS characteristics. For the CV curve fitting, mainly this paper approximates the measured CVdata as a piecewise function, and then expresses the function with the sub-circuit form, finallysimulates the sub-circuit model by Cadence. It is found that the fitting accuracy of the sub-circuit model is high, and the error between measured data and simulated data is small.