Research On Key Technology For Solid State Drive Design

The computer system has made a great progress in various aspects after decades ofdevelopment. The capacity of hard disk has improved enormously; however, compared with othercomponents of computer (such as memory and processor), the problem of access speed mismatchbetween hard disk and processor becomes more seriously, which makes the storage subsystembecomes the bottleneck of computer performance. The emergence of NAND flash-based Solid StateDrive (SSD) relieves the trouble in a certain degree. Due to the inherent defects of SSD, there arealso many disadvantages within NAND flash-based SSD, such as large speed gap between read andwrite operation, non-support for in-place update, limited program/erase times, which seriouslyaffect its performance, lifespan and reliability. Focusing on NAND flash-based SSD design, westudy two problems: one is flash translation layer (FTL) and the other is buffer management in SSDdesign.In the study of FTL design, we propose a page-mapping-based FTL, called SDFTL(Sequential/Second Cache DFTL). By analyzing the defects of tranditional DFTL algorithm,SDFTL adds a sequential cache and a second-level cache on the basis of DFTL, which can enhancethe performance of DFTL for the sequential requests and can reduce the update counts arised by thefrequently evict-out of map entries. In SDFTL, the sequential cache improves the cache hit ratio andreduces the read and write counts of translation page by prefetching map entries to exploit thespatial locality of workloads. The second-level cache reduces the write and erase counts oftranslation page by improving the evict strategy of mapping information, which delays the updatetime of map entries and employs batch updating strategy by buffering the map entries evicted fromthe first-level cache. By the above to innovations, the SDFTL algorithm can significantly improvethe performance of handling the sequential requests and reduce the system average response time.The simulation results show that SDFTL can improve the mapping entry hit ratio41.57%andreduce the erase counts23.08%and response time17.74%compared with those of DFTL inaverage.In the study of buffer management design, we propose a virtual-block-based write buffer(VBLRU) management algorithm by analyzing the defects of BPLRU algorithm. Firstly, VBLRUuses the virtual block as the basic unit of buffer management, which can increase the possibility toform sequential requests, to reduce the additional read and write operations during evicting cacheentries of BPLRU; Secondly, for large and sequential write requests, VBLRU send them to FTL directly, and thus increase the utilization ratio of buffer. By the above improvements, the VBLRUalgorithm can significantly reduce the read and write counts, improve the utilization ratio of bufferand the overall system performance. The simulation results show that VBLRU can improve thewrite buffer hit ratio7.25%and reduce the erase counts31.64%and response time22.50%compared with those of BPLRU in average with buffer size of1MB.