Studying And Optimization Of The ESD Robustness Of LDMOS Device Based On0.35μm40V BCD Process

In the semiconductor industry, with the improvement of integrated circuit’sintegration and the reduction of device feature size, the potential damage induced byelectrostatic discharge (ESD) to the IC chip has become more and more serious. Withdifferent process, the influence of various parameters to the device is different. What’smore, with different device structure, the influence of various parameters to the devicealso exists difference. So, it’s very important to study the effect of various parameters tothe ESD protection devices under specific process.In this paper, we have studied the ESD characteristics of a GG-NLDMOS (GateGrounded n-type lateral diffused MOS) device under0.35μm40V BCD process. Firstlythis paper introduces design mechanism and working principle of basic ESD protectiondevices and the ESD test models. Then this paper has studied TLP (Transmission LinePulse) test results of the original GG-NLDMOS and found that the originalGG-NLDMOS device exists serious non-uniformly turn on characteristic. And then theworking characteristics of the original GG-NLDMOS device under ESD stress havebeen studied by TSUPREM4and MEDICI simulation software. Then, the effects ofvarious parameters to the GG-NLDMOS are studied. They include channel length、LOCOS length of Drain、substrate resistance and plate length in the active region. Thesubstrate resistance is changed by changing the distance between substrate contact andN+region of the source and reducing the area of the substrate contact. This paper hasalso studied the SCR (Silicon Controlled Rectifier) based on the NLDMOS and theconduction condition of the parasitic SCR through simulation and TLP test results.Finally, the optimization technique of the GG-NLDMOS device layout is introduced,including isolation optimization、the rush of active region optimization and metal lineoptimization.With the above research, this paper has successfully improved the turn onuniformity and the ESD robustness of the GG-NLDMOS device.