Design Of Low Power Vector Process Element And Research Of Reduce Network In YHFT-Matrix DSP

Digital signal processor （DSP） is a class of embedded microprocessors which is verysuitable for digital signal processing.As a key component in many multimedia appliances andcommunication devices, DSP is required for higher performance.So it has more value onresearch and applications.This thesis takes the design of “YHFT-Matrix DSP” for thebackground,research the high performance vector process element（VPE） and reduce networkwhich are suitable for YHFT-Matrix DSP.Analyse the architecture characteristics of DSP, vector computing technologies, andintroduce the international DSPs for3G or4G wireless communication with relative vectorcomputing technologies. Introduce the architecture of YHFT-Matrix DSP and the features ofVPE and vector data passing networks; conclude that designing VPE, the power of which shouldbe optimized with low power technologies and vector data passing networks should be smart andconveniently used; propose the worthy improvement of computing units according to users.Introduce the hierarchical low power design methods and low power technologies of RTLclass. Implement vector process unit（VPU） with various vector width by clock gating.AnalyseSIMD IALU function and relative instructions, design its microarchitecture; taking thecarry_selected SIMD adder as a core module, implement SIMD IALU with operand isolating.Based on radix₄apart divide algorithm and state assignment, design a fixed divider, whichsupports signed and unsigned division and8/16/32bits SISD/SIMD modes; it has two executemodes of constant cycles and various cycles, which are suitable for VPU and SPU.Illustrating by matrix multiplication, analyse and compare reduce operation by software andhardware, and indicate that hardware can accelerate program with extra area cost. Design andimplement a fixed reduce network which supports average grouping by adopting a hierarchicalreduce tree and loop programming by implicitly auto specifying destination VPE. Research theimplementation of float reduce network, and the conclusion is that because of heavy area cost offloat calculate unit, bring in hardware-software codesign to realize float reduce operation.Propose a design scheme supporting hybrid float reduce operation that scheduling by controllogic, a shuffle network moves vector operands to float calculating array in relative VPEs, andthe calculating array reduce the vector operands to a scaler result.Introduce the logical function verification flow of YHFT-Matrix DSP, and give the detaildescription of module verification platform based on Verilog HDL and Perl. Make logicsynthesis of above function units in TSMC65nm library by DC, and give the results of synthesisand analysis of performance showing the frequency reaches700MHz. Give a brief introductionabout the emulation of YHFT-QMBase and performance evaluation of YHFT-Matrix DSP.