Key Techniques Research Of Memory In Homogeneous General Purpose Stream Processor

The enhanced demand for applications based on processors has promoted theemerging evolution of processor architecture, and inspired remarkable innovationsonprocessor design. Multi-core Stream Processor which consists of plenty ofsimple-archcores is a new kind of Multi-core Processor for the streaming dataprocessing and streaming applications.Compared with traditional processors, multi-coreStream Processor is designed for compute-intensive applications which generate highthroughput and resource utilization rate, however, the performance declines when facedwithmemory-access-intensive applications and sparse applications. Besides, the Cachehierarchy cannot facilitate the data locality characteristics of the streaming applications.To fulfill the demand on both the streaming and sparse applications, the HomogeneousGeneral Purpose Stream Processor (HGPSP) architecture merging stream and traditionalarchitecture is proposed. It is constructed with a few stream multi-core processors whichis configurable to be a CPU or GPU depend on specific applications. There is somedifference between CPU’s and GPU’s storage hierarch, the former is a Cache-basedon-chip cache structure, while the latter constitute withregister file and on-chipScratch-Padmemory. The architecture is configured by adjusting the ratio of theScratch-Pad Memory and the Cache whichshare the common on-chip memory resources.The Cache meets the requirementsof CPU’s applications, facilitating its time and spacelocality. While the Scratch-Pad Memory makes use of the Producer-Consumer localityin the streaming applications.This subject aims at in-depth research on the key technologies about the streammulti-core architecture’s memory accessing; the major works and innovations list asfollows:1. A configurable on-chip shared SPM/L2Cache structure is proposed. Accordingto the applications’ demand, the basic unit of HGPSP, stream multi-core processor, canoperate on on-chip SMP execution mode or the SIMT execution mode. Under differentexecution modes, on-chip shared memory is configured separately to meet theprocessor’s demand on storage unit.2. A new cache coherence protocol for the L1D and L2Cache of the streammulti-core processor is designed. The write-through strategy is used in the private L1D,and the write-back strategy is used in the shared L2cache. The data coherence betweenthe two level caches is maintained through invaliding the copy of the modifiedcacheline under this situation.3. Designed the private L1Cache for Stream core. Extend the32-bit width datacache model of the Microblaze soft core into64-bit and add the coherence maintenancelogic circuit, we accomplish the design of the inner buffer structure for the Stream architecture.4. Simulate and analysis the performance of the key unit of the logical designs ofmemory accessing based on the Xilinx’s software. Results demonstrates that all thedesign goals were achieved and the performance analysis has showed the effectivenessof the proposed design.